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1997 microchip technology inc. ds30234d-page 1 pic16c6x 8-bit cmos microcontrollers devices included in this data sheet: pic16c6x microcontroller core features: high performance risc cpu only 35 single word instructions to learn all single cycle instructions except for program branches which are two-cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle interrupt capability eight level deep hardware stack direct, indirect, and relative addressing modes power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode selectable oscillator options pic16c61 pic16c64a pic16c62 pic16cr64 pic16c62a pic16c65 pic16cr62 pic16c65a pic16c63 pic16cr65 pic16cr63 pic16c66 pic16c64 pic16c67 low-power, high-speed cmos eprom/rom technology fully static design wide operating voltage range: 2.5v to 6.0v commercial, industrial, and extended temperature ranges low-power consumption: < 2 ma @ 5v, 4 mhz 15 m a typical @ 3v, 32 khz < 1 m a typical standby current pic16c6x peripheral features: timer0: 8-bit timer/counter with 8-bit prescaler timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler capture/compare/pwm (ccp) module(s) capture is 16-bit, max resolution is 12.5 ns, compare is 16-bit, max resolution is 200 ns, pwm max resolution is 10-bit. synchronous serial port (ssp) with spi ? and i 2 c ? universal synchronous asynchronous receiver transmitter (usart/sci) parallel slave port (psp) 8-bits wide, with external rd , wr and cs controls brown-out detection circuitry for brown-out reset (bor) pic16c6x features 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 program memory (eprom) x 14 1k 2k 2k 4k 2k 2k 4k 4k 8k 8k (rom) x 14 2k 4k 2k 4k data memory (bytes) x 8 36 128 128 128 192 192 128 128 128 192 192 192 368 368 i/o pins 13 22 22 22 22 22 33 33 33 33 33 33 22 33 parallel slave port yesyesyesyes yes yes yes capture/compare/pwm module(s) 1112211122222 timer modules 1333 3 3 333 33333 serial communication spi/ i 2 c spi/ i 2 c spi/ i 2 c spi/i 2 c, usart spi/i 2 c, usart spi/ i 2 c spi/ i 2 c spi/ i 2 c spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart in-circuit serial programming ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s brown-out reset yes yes yes yes yes yes yes yes yes yes interrupt sources 3777 10 10 888 11 11 11 10 11 sink/source current (ma) 25/20 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25
pic16c6x ds30234d-page 2 1997 microchip technology inc. pin diagrams pdip, soic, windowed cerdip 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 pic16c61 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss v ss osc1/clkin osc2/clkout rc0/t1osi/t1cki rc1/t1oso 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c62 rc2/ccp1 rc3/sck/scl sdip, soic, ssop, windowed cerdip (300 mil) ra2 ra3 ra4/t0cki mclr /v pp v ss rb0/int rb1 rb2 rb3 ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c63 rc2/ccp1 rc3/sck/scl sdip, soic, windowed cerdip (300 mil) rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c62a rc2/ccp1 rc3/sck/scl sdip, soic, ssop, windowed cerdip (300 mil) pic16cr62 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c65 pdip, windowed cerdip rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7 rc6 rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin osc2/clkout rc0/t1osi/t1cki rc1/t1oso rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c64 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7 rc6 rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c64a pic16c65a pic16cr64 pic16cr63 pic16cr65 pic16c66 pic16c67
1997 microchip technology inc. ds30234d-page 3 pic16c6x pin diagrams (cont.d) nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs re1/wr re0/rd ra5/ss ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3 ra2 ra1 ra0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 pic16c65 mqfp, rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin osc2/clkout nc ra3 ra2 ra1 ra0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 pic16c65 /ccp2 plcc rc0/t1oso/t1cki nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs re1/wr re0/rd ra5/ss ra4/t0cki rc7 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6 rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3 ra2 ra1 ra0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 34 35 36 37 38 39 40 41 42 43 44 pic16c64a mqfp, rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7 ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin osc2/clkout nc ra3 ra2 ra1 ra0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6 rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 pic16c64a plcc rc0/t1oso/t1cki pic16cr64 pic16cr64 pic16c65a pic16c65a tqfp (pic16c64a only) tqfp (not on pic16c65) rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7 ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin nc ra3 ra2 ra1 ra0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6 rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1oso 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 pic16c64 plcc nc rc0/t1osi/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs re1/wr re0/rd ra5/ss ra4/t0cki rc7 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6 rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1oso nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3 ra2 ra1 ra0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 pic16c64 mqfp rc0/t1osi/t1cki osc2/clkout 22 21 20 19 18 17 16 15 14 13 12 pic16cr65 pic16cr65 pic16c67 pic16c67
pic16c6x ds30234d-page 4 1997 microchip technology inc. table of contents 1.0 general description ......................................................................................................... .............................................................. 5 2.0 pic16c6x device varieties ................................................................................................... ........................................................ 7 3.0 architectural overview ...................................................................................................... ............................................................. 9 4.0 memory organization......................................................................................................... .......................................................... 19 5.0 i/o ports................................................................................................................... .................................................................... 51 6.0 overview of timer modules ................................................................................................... ...................................................... 63 7.0 timer0 module ............................................................................................................... .............................................................. 65 8.0 timer1 module ............................................................................................................... .............................................................. 71 9.0 timer2 module ............................................................................................................... .............................................................. 75 10.0 capture/compare/pwm (ccp) module(s)........................................................................................ ........................................... 77 11.0 synchronous serial port (ssp) module....................................................................................... ................................................ 83 12.0 universal synchronous asynchronous receiver transmitter (usart) module ..................................................... .................. 105 13.0 special features of the cpu ................................................................................................ ..................................................... 123 14.0 instruction set summary.................................................................................................... ........................................................ 143 15.0 development support ........................................................................................................ ........................................................ 159 16.0 electrical characteristics for pic16c61 .................................................................................... ................................................. 163 17.0 dc and ac characteristics graphs and tables for pic16c61................................................................... ............................... 173 18.0 electrical characteristics for pic16c62/64................................................................................. ............................................... 183 19.0 electrical characteristics for pic16c62a/r62/64a/r64....................................................................... ..................................... 199 20.0 electrical characteristics for pic16c65 .................................................................................... ................................................. 215 21.0 electrical characteristics for pic16c63/65a ................................................................................ ............................................. 231 22.0 electrical characteristics for pic16cr63/r65............................................................................... ............................................ 247 23.0 electrical characteristics for pic16c66/67................................................................................. ............................................... 263 24.0 dc and ac characteristics graphs and tables for: pic16c62, pic16c62a, pic16cr62, pic16c63, pic16c64, pic16c64a, pic16cr64, pic16c65a, pic16c66, pic16c67.................................................................................................. ......................................... 281 25.0 packaging information ...................................................................................................... ......................................................... 291 appendix a: modifications....................................................................................................... ....................................................... 307 appendix b: compatibility ....................................................................................................... ....................................................... 307 appendix c: what? new.......................................................................................................... ...................................................... 308 appendix d: what? changed ...................................................................................................... .................................................. 308 appendix e: pic16/17 microcontrollers ......................................................................................... .............................................. 309 pin compatibility .............................................................................................................. .................................................................. 315 index .......................................................................................................................... ........................................................................ 317 list of equation and examples.................................................................................................. ......................................................... 326 list of figures................................................................................................................ ..................................................................... 326 list of tables................................................................................................................. ..................................................................... 330 reader response ................................................................................................................ .............................................................. 334 pic16c6x product identification system......................................................................................... .................................................. 335 for register and module descriptions in this data sheet, device legends show which devices apply to those sections. for example, the legend below shows that some features of only the pic16c62a, pic16cr62, pic16c63, pic16c64a, pic16cr64, and pic16c65a are described in this section. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent an exceptional amount of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you ?d any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a better document.
1997 microchip technology inc. ds30234d-page 5 pic16c6x 1.0 general description the pic16cxx is a family of low-cost, high-perfor- mance, cmos, fully-static, 8-bit microcontrollers. all pic16/17 microcontrollers employ an advanced risc architecture. the pic16cxx microcontroller fam- ily has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with separate 8-bit wide data. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). a total of 35 instructions (reduced instruction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. pic16cxx microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. the pic16c61 device has 36 bytes of ram and 13 i/o pins. in addition a timer/counter is available. the pic16c62/62a/r62 devices have 128 bytes of ram and 22 i/o pins. in addition, several peripheral features are available, including: three timer/counters, one capture/compare/pwm module and one serial port. the synchronous serial port can be con?ured as either a 3-wire serial peripheral interface (spi ? ) or the two-wire inter-integrated circuit (i 2 c) bus. the pic16c63/r63 devices have 192 bytes of ram, while the pic16c66 has 368 bytes. all three devices have 22 i/o pins. in addition, several peripheral fea- tures are available, including: three timer/counters, two capture/compare/pwm modules and two serial ports. the synchronous serial port can be con?ured as either a 3-wire serial peripheral interface (spi) or the two-wire inter-integrated circuit (i 2 c) bus. the univer- sal synchronous asynchronous receiver transmitter (usart) is also know as a serial communications interface or sci. the pic16c64/64a/r64 devices have 128 bytes of ram and 33 i/o pins. in addition, several peripheral features are available, including: three timer/counters, one capture/compare/pwm module and one serial port. the synchronous serial port can be con?ured as either a 3-wire serial peripheral interface (spi) or the two-wire inter-integrated circuit (i 2 c) bus. an 8-bit parallel slave port is also provided. the pic16c65/65a/r65 devices have 192 bytes of ram, while the pic16c67 has 368 bytes. all four devices have 33 i/o pins. in addition, several peripheral features are available, including: three timer/counters, two capture/compare/pwm modules and two serial ports. the synchronous serial port can be con?ured as either a 3-wire serial peripheral interface (spi) or the two-wire inter-integrated circuit (i 2 c) bus. the uni- versal synchronous asynchronous receiver transmit- ter (usart) is also known as a serial communications interface or sci. an 8-bit parallel slave port is also pro- vided. the pic16c6x device family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power con- sumption. there are four oscillator options, of which the single pin rc oscillator provides a low-cost solution, the lp oscillator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crystals. the sleep (power-down) mode offers a power saving mode. the user can wake the chip from sleep through several external and internal interrupts, and resets. a highly reliable watchdog timer with its own on-chip rc oscillator provides protection against software lock- up. a uv erasable cerdip packaged version is ideal for code development, while the cost-effective one-time-programmable (otp) version is suitable for production in any volume. the pic16c6x family ?s perfectly in applications rang- ing from high-speed automotive and appliance control to low-power remote sensors, keyboards and telecom processors. the eprom technology makes customi- zation of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. the small footprint packages make this microcontroller series perfect for all applica- tions with space limitations. low-cost, low-power, high performance, ease-of-use, and i/o ?xibility make the pic16c6x very versatile even in areas where no micro- controller use has been considered before (e.g. timer functions, serial communication, capture and compare, pwm functions, and co-processor applications). 1.1 f amil y and upwar d c ompatibility those users familiar with the pic16c5x family of microcontrollers will realize that this is an enhanced version of the pic16c5x architecture. please refer to appendix a for a detailed list of enhancements. code written for pic16c5x can be easily ported to pic16cxx family of devices (appendix b). 1.2 de velopment suppor t pic16c6x devices are supported by the complete line of microchip development tools. please refer to section 15.0 for more details about microchips development tools.
pic16c6x ds30234d-page 6 1997 microchip technology inc. table 1-1: pic16c6x family of devices pic16c61 pic16c62a pic16cr62 pic16c63 pic16cr63 clock maximum frequency of operation (mhz) 20 20 20 20 20 memory eprom program memory (x14 words) 1k 2k 4k rom program memory (x14 words) 2k 4k data memory (bytes) 36 128 128 192 192 peripherals timer module(s) tmr0 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/ pwm module(s) 1122 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c spi/i 2 c, usart spi/i 2 c usart parallel slave port features interrupt sources 3 7 7 10 10 i/o pins 13 22 22 22 22 voltage range (volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 in-circuit serial programming yes yes yes yes yes brown-out reset yes yes yes yes packages 18-pin dip, so 28-pin sdip, soic, ssop 28-pin sdip, soic, ssop 28-pin sdip, soic 28-pin sdip, soic pic16c64a pic16cr64 pic16c65a pic16cr65 pic16c66 pic16c67 clock maximum frequency of operation (mhz) 20 20 20 20 20 20 memory eprom program memory (x14 words) 2k 4k 8k 8k rom program memory (x14 words) ?k 4k data memory (bytes) 128 128 192 192 368 368 peripherals timer module(s) tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm mod- ule(s) 1 1 2 222 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart parallel slave port yes yes yes yes yes features interrupt sources 8 8 11 11 10 11 i/o pins 33 33 33 33 22 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 in-circuit serial programming yes yes yes yes yes yes brown-out reset yes yes yes yes yes yes packages 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 28-pin sdip, soic 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c6x family devices use serial programming with clock pin rb6 and data pin rb7.
1997 microchip technology inc. ds30234d-page 7 pic16c6x 2.0 pic16c6x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic16c6x product identi? cation system section at the end of this data sheet. when placing orders, please use that page of the data sheet to specify the correct part number. for the pic16c6x family of devices, there are four device ?ypes as indicated in the device number: 1. c , as in pic16 c 64. these devices have eprom type memory and operate over the standard voltage range. 2. lc , as in pic16 lc 64. these devices have eprom type memory and operate over an extended voltage range. 3. cr , as in pic16 cr 64. these devices have rom program memory and operate over the standard voltage range. 4. lcr , as in pic16 lcr 64. these devices have rom program memory and operate over an extended voltage range. 2.1 uv erasab le de vice s the uv erasable version, offered in cerdip package is optimal for prototype development and pilot programs. this version can be erased and reprogrammed to any of the oscillator modes. microchip's picstart plus and pro mate ii programmers both support programming of the pic16c6x. 2.2 o ne-time-pr ogrammab le (o tp) de vices the availability of otp devices is especially useful for customers who need the ?xibility for frequent code updates and small volume applications. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the con?uration bits must also be programmed. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and con?uration options already programmed by the factory. certain code and prototype veri?ation procedures apply before produc- tion shipments are available. please contact your local microchip technology sales of?e for more details. 2.4 serializ ed quic k-t urnar ound pr oduction (sqtp sm ) de vices microchip offers a unique programming service where a few user-de?ed locations in each device are pro- grammed with different serial numbers. the serial num- bers may be random, pseudo-random, or sequential. serial programming allows each device to have a unique number which can serve as an entry-code, password, or id number. rom devices do not allow serialization information in the program memory space. the user may have this information programmed in the data memory space. for information on submitting rom code, please con- tact your regional sales of?e. 2.5 read onl y memor y (r om) de vices microchip offers masked rom versions of several of the highest volume parts, thus giving customers a low cost option for high volume, mature products. for information on submitting rom code, please con- tact your regional sales of?e.
pic16c6x ds30234d-page 8 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30234d-page 9 pic16c6x 3.0 architectural overview the high performance of the pic16cxx family can be attributed to a number of architectural features com- monly found in risc microprocessors. to begin with, the pic16cxx uses a harvard architecture, in which, program and data are accessed from separate memo- ries using separate buses. this improves bandwidth over traditional von neumann architecture where pro- gram and data may be fetched from the same memory using the same bus. separating program and data bus- ses further allows instructions to be sized differently than 8-bit wide data words. instruction opcodes are 14-bits wide making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. a two- stage pipeline overlaps fetch and execution of instruc- tions (example 3-1). consequently, all instructions exe- cute in a single cycle (200 ns @ 20 mhz) except for program branches. the pic16c61 addresses 1k x 14 of program memory. the pic16c62/62a/r62/64/64a/r64 address 2k x 14 of program memory, and the pic16c63/r63/65/65a/r65 devices address 4k x 14 of program memory. the pic16c66/67 address 8k x 14 program memory. all program memory is internal. the pic16cxx can directly or indirectly address its register ?es or data memory. all special function reg- isters including the program counter are mapped in the data memory. the pic16cxx has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?pecial optimal situations makes programming with the pic16cxx simple yet ef?ient, thus signi?antly reducing the learning curve. the pic16cxx device contains an 8-bit alu and work- ing register (w). the alu is a general purpose arith- metic unit. it performs arithmetic and boolean functions between data in the working register and any register ?e. the alu is 8-bits wide and capable of addition, sub- traction, shift, and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the working register (w register), the other operand is a ?e register or an immediate con- stant. in single operand instructions, the operand is either the w register or a ?e register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending upon the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. bits c and dc operate as a borro w and digit b orro w out bit, respec- tively, in subtraction. see the sublw and subwf instructions for examples.
pic16c6x ds30234d-page 10 1997 microchip technology inc. figure 3-1: pic16c61 block diagram eprom program memory 1k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 36 x 8 direct addr 7 9 addr mux indirect addr 8 fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss timer0 3 porta portb ra1 ra4/t0cki rb0/int rb7:rb1 8 8 ram addr (1) note 1: higher order bits are from the status register. ra0 ra2 ra3
1997 microchip technology inc. ds30234d-page 11 pic16c6x figure 3-2: pic16c62/62a/r62/64/64a/r64 block diagram eprom/ program memory 2k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 128 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr 8 fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss synchronous serial port 3 porta portb portc portd porte ra4/t0cki ra5/ss rb0/int rb7:rb1 rc0/t1oso/t1cki (4) rc1/t1osi (4) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6 rc7 re0/rd re1/wr re2/cs rd0/psp0 8 8 (note 2) brown-out reset (3) rom timer0 timer1 timer2 ccp1 ra1 ra0 ra2 ra3 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 parallel slave port note 1: higher order bits are from the status register. 2: portd, porte and the parallel slave port are not available on the pic16c62/62a/r62. 3: brown-out reset is not available on the pic16c62/64. 4: pin functions t1osi and t1oso are swapped on the pic16c62/64.
pic16c6x ds30234d-page 12 1997 microchip technology inc. figure 3-3: pic16c63/r63/65/65a/r65 block diagram synchronous serial port eprom program memory 4k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 192 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr 8 fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss 3 porta portb portc portd porte ra4/t0cki ra5/ss rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt re0/rd re1/wr re2/cs 8 8 brown-out reset (3) (note 2) usart timer0 timer1 timer2 ccp2 ccp1 rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 ra1 ra0 ra2 ra3 parallel slave port note 1: higher order bits are from the status register. 2: portd, porte and the parallel slave port are not available on the pic16c63/r63. 3: brown-out reset is not available on the pic16c65.
1997 microchip technology inc. ds30234d-page 13 pic16c6x figure 3-4: pic16c66/67 block diagram synchronous serial port eprom program memory 8k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 368 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr 8 fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss 3 porta portb portc portd porte ra4/t0cki ra5/ss rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt re0/rd re1/wr re2/cs 8 8 brown-out reset (note 2) usart timer0 timer1 timer2 ccp2 ccp1 rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 ra1 ra0 ra2 ra3 parallel slave port note 1: higher order bits are from the status register. 2: portd, porte and the parallel slave port are not available on the pic16c66.
pic16c6x ds30234d-page 14 1997 microchip technology inc. table 3-1: pic16c61 pinout description pin name dip pin# soic pin# pin type buffer type description osc1/clkin 16 16 i st/cmos (1) oscillator crystal input/external clock source input. osc2/clkout 15 15 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 4 4 i/p st master clear reset input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0 17 17 i/o ttl ra1 18 18 i/o ttl ra2 1 1 i/o ttl ra3 2 2 i/o ttl ra4/t0cki 3 3 i/o st ra4 can also be the clock input to the timer0 timer/counter. output is open drain type. portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-up on all inputs. rb0/int 6 6 i/o ttl/st (2) rb0 can also be the external interrupt pin. rb1 7 7 i/o ttl rb2 8 8 i/o ttl rb3 9 9 i/o ttl rb4 10 10 i/o ttl interrupt on change pin. rb5 11 11 i/o ttl interrupt on change pin. rb6 12 12 i/o ttl/st (3) interrupt on change pin. serial programming clock. rb7 13 13 i/o ttl/st (3) interrupt on change pin. serial programming data. v ss 5 5 p ground reference for logic and i/o pins. v dd 14 14 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise. 2: this buffer is a schmitt trigger input when con?ured as the external interrupt. 3: this buffer is a schmitt trigger input when used in serial programming mode.
1997 microchip technology inc. ds30234d-page 15 pic16c6x table 3-2: pic16c62/62a/r62/63/r63/66 pinout description pin name pin# pin type buffer type description osc1/clkin 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 o oscillator crystal output. connects to crystal or resonator in crys- tal oscillator mode. in rc mode, the pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. m clr /v pp 1 i/p st master clear reset input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0 2 i/o ttl ra1 3 i/o ttl ra2 4 i/o ttl ra3 5 i/o ttl ra4/t0cki 6 i/o st ra4 can also be the clock input to the timer0 timer/counter. output is open drain type. ra5/ss 7 i/o ttl ra5 can also be the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-up on all inputs. rb0/int 21 i/o ttl/st (4) rb0 can also be the external interrupt pin. rb1 22 i/o ttl rb2 23 i/o ttl rb3 24 i/o ttl rb4 25 i/o ttl interrupt on change pin. rb5 26 i/o ttl interrupt on change pin. rb6 27 i/o ttl/st (5) interrupt on change pin. serial programming clock. rb7 28 i/o ttl/st (5) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso (1) /t1cki 11 i/o st rc0 can also be the timer1 oscillator output (1) or timer1 clock input. rc1/t1osi (1) /ccp2 (2) 12 i/o st rc1 can also be the timer1 oscillator input (1) or capture2 input/compare2 output/pwm2 output (2) . rc2/ccp1 13 i/o st rc2 can also be the capture1 input/compare1 out- put/pwm1 output. rc3/sck/scl 14 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck (2) 17 i/o st rc6 can also be the usart asynchronous transmit (2) or synchronous clock (2) . rc7/rx/dt (2) 18 i/o st rc7 can also be the usart asynchronous receive (2) or synchronous data (2) . v ss 8,19 p ground reference for logic and i/o pins. v dd 20 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: pin functions t1oso and t1osi are reversed on the pic16c62. 2: the usart and ccp2 are not available on the pic16c62/62a/r62. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise. 4: this buffer is a schmitt trigger input when con?ured as the external interrupt. 5: this buffer is a schmitt trigger input when used in serial programming mode.
pic16c6x ds30234d-page 16 1997 microchip technology inc. table 3-3: pic16c64/64a/r64/65/65a/r65/67 pinout description pin name dip pin# plcc pin# tqfp mqfp pin# pin type buffer type description osc1/clkin 13 14 30 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 14 15 31 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the pin outputs clk- out which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 2 18 i/p st master clear reset input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0 2 3 19 i/o ttl ra1 3 4 20 i/o ttl ra2 4 5 21 i/o ttl ra3 5 6 22 i/o ttl ra4/t0cki 6 7 23 i/o st ra4 can also be the clock input to the timer0 timer/counter. output is open drain type. ra5/ss 7 8 24 i/o ttl ra5 can also be the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 33 36 8 i/o ttl/st (4) rb0 can also be the external interrupt pin. rb1 34 37 9 i/o ttl rb2 35 38 10 i/o ttl rb3 36 39 11 i/o ttl rb4 37 41 14 i/o ttl interrupt on change pin. rb5 38 42 15 i/o ttl interrupt on change pin. rb6 39 43 16 i/o ttl/st (5) interrupt on change pin. serial programming clock. rb7 40 44 17 i/o ttl/st (5) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso (1) /t1cki 15 16 32 i/o st rc0 can also be the timer1 oscillator output (1) or timer1 clock input. rc1/t1osi (1) /ccp2 (2) 16 18 35 i/o st rc1 can also be the timer1 oscillator input (1) or capture2 input/compare2 output/pwm2 output (2) . rc2/ccp1 17 19 36 i/o st rc2 can also be the capture1 input/compare1 out- put/pwm1 output. rc3/sck/scl 18 20 37 i/o st rc3 can also be the synchronous serial clock input/out- put for both spi and i 2 c modes. rc4/sdi/sda 23 25 42 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 24 26 43 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck (2) 25 27 44 i/o st rc6 can also be the usart asynchronous transmit (2) or synchronous clock (2) . rc7/rx/dt (2) 26 29 1 i/o st rc7 can also be the usart asynchronous receive (2) or synchronous data (2) . legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: pin functions t1oso and t1osi are reversed on the pic16c64. 2: ccp2 and the usart are not available on the pic16c64/64a/r64. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise. 4: this buffer is a schmitt trigger input when con?ured as the external interrupt. 5: this buffer is a schmitt trigger input when used in serial programming mode. 6: this buffer is a schmitt trigger input when con?ured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus).
1997 microchip technology inc. ds30234d-page 17 pic16c6x portd can be a bi-directional i/o port or parallel slave port for interfacing to a microprocessor bus. rd0/psp0 19 21 38 i/o st/ttl (6) rd1/psp1 20 22 39 i/o st/ttl (6) rd2/psp2 21 23 40 i/o st/ttl (6) rd3/psp3 22 24 41 i/o st/ttl (6) rd4/psp4 27 30 2 i/o st/ttl (6) rd5/psp5 28 31 3 i/o st/ttl (6) rd6/psp6 29 32 4 i/o st/ttl (6) rd7/psp7 30 33 5 i/o st/ttl (6) porte is a bi-directional i/o port. re0/rd 8 9 25 i/o st/ttl (6) re0 can also be read control for the parallel slave port. re1/wr 9 10 26 i/o st/ttl (6) re1 can also be write control for the parallel slave port. re2/cs 10 11 27 i/o st/ttl (6) re2 can also be select control for the parallel slave port. v ss 12,31 13,34 6,29 p ground reference for logic and i/o pins. v dd 11,32 12,35 7,28 p positive supply for logic and i/o pins. nc 1,17, 28,40 12,13, 33,34 these pins are not internally connected. these pins should be left unconnected. table 3-3: pic16c64/64a/r64/65/65a/r65/67 pinout description (cont.d) pin name dip pin# plcc pin# tqfp mqfp pin# pin type buffer type description legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: pin functions t1oso and t1osi are reversed on the pic16c64. 2: ccp2 and the usart are not available on the pic16c64/64a/r64. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise. 4: this buffer is a schmitt trigger input when con?ured as the external interrupt. 5: this buffer is a schmitt trigger input when used in serial programming mode. 6: this buffer is a schmitt trigger input when con?ured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus).
pic16c6x ds30234d-page 18 1997 microchip technology inc. 3.1 cloc king sc heme/ instruction cyc le the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3, and q4. internally, the pro- gram counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clock and instruction execution ?w is shown in figure 3-5. 3.2 instruction flo w/pipelining an ?nstruction cycle consists of four q cycles (q1, q2, q3, and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g. goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?nstruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-5: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc (program counter) osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed from the pipeline while the new instruction is being fetched and then executed. tcy0 tcy1 tcy2 tcy3 tcy4 tcy5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
1997 microchip technology inc. ds30234d-page 19 pic16c6x 4.0 memory organization 4.1 pr ogram memor y or ganization the pic16c6x family has a 13-bit program counter capable of addressing an 8k x 14 program memory space. the amount of program memory available to each device is listed below: for those devices with less than 8k program memory, accessing a location above the physically implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 4-1: pic16c61 program memory map and stack applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 device program memory address range pic16c61 1k x 14 0000h-03ffh pic16c62 2k x 14 0000h-07ffh pic16c62a 2k x 14 0000h-07ffh pic16cr62 2k x 14 0000h-07ffh pic16c63 4k x 14 0000h-0fffh pic16cr63 4k x 14 0000h-0fffh pic16c64 2k x 14 0000h-07ffh pic16c64a 2k x 14 0000h-07ffh pic16cr64 2k x 14 0000h-07ffh pic16c65 4k x 14 0000h-0fffh pic16c65a 4k x 14 0000h-0fffh pic16cr65 4k x 14 0000h-0fffh pic16c66 8k x 14 0000h-1fffh pic16c67 8k x 14 0000h-1fffh pc<12:0> stack level 1 stack level 8 user memory space call, return retfie, retlw 13 0000h 0004h 1fffh 03ffh 0400h on-chip program memory 0005h reset vector peripheral interrupt vector figure 4-2: pic16c62/62a/r62/64/64a/ r64 program memory map and stack figure 4-3: pic16c63/r63/65/65a/r65 program memory map and stack pc<12:0> stack level 1 stack level 8 user memory space call, return retfie, retlw 13 0000h 0004h 1fffh 07ffh 0800h on-chip program memory 0005h reset vector peripheral interrupt vector pc<12:0> stack level 1 stack level 8 user memory space call, return retfie, retlw 13 0000h 0004h 1fffh 07ffh 0fffh 0800h 1000h on-chip program memory (page 0) on-chip program memory (page 1) 0005h reset vector peripheral interrupt vector
pic16c6x ds30234d-page 20 1997 microchip technology inc. figure 4-4: pic16c66/67 program memory map and stack 4.2 d ata memor y or ganization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1 and rp0 are the bank select bits. rp1:rp0 (status<6:5>) = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 = 11 ? bank3 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some ?igh use special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 4.2.1 general purpose registers these registers are accessed either directly or indi- rectly through the file select register (fsr) (section 4.5). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 pc<12:0> stack level 1 stack level 8 user memory space call, return retfie, retlw 13 0000h 0004h 0fffh 1000h on-chip program memory (page 0) on-chip program memory (page 1) 0005h reset vector peripheral interrupt vector 07ffh 0800h on-chip program memory (page 2) on-chip program memory (page 3) 17ffh 1800h 1fffh for the pic16c61, general purpose register locations 8ch-afh of bank 1 are not physically implemented. these locations are mapped into 0ch-2fh of bank 0. figure 4-5: pic16c61 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 2fh 30h 7fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch afh b0h ffh bank 0 bank 1 indf (1) indf (1) tmr0 option pcl status fsr porta portb pclath intcon general purpose register pcl status fsr trisa trisb pclath intcon mapped in bank 0 (2) unimplemented data memory location; read as '0'. note 1: not a physical register. 2: these locations are unimplemented in bank 1. any access to these locations will access the corresponding bank 0 register. file address
1997 microchip technology inc. ds30234d-page 21 pic16c6x figure 4-6: pic16c62/62a/r62/64/64a/ r64 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 7fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch ffh bank 0 bank 1 indf (1) indf (1) tmr0 option pcl status fsr porta portb portd (2) porte (2) pclath intcon pcl status fsr trisa trisb trisd (2) trise (2) pclath intcon unimplemented data memory location; read as '0'. portc trisc pir1 pie1 tmr1l pcon tmr1h t1con tmr2 t2con pr2 sspbuf sspadd sspstat sspcon ccpr1l ccpr1h ccp1con general purpose register 0dh 8dh 0eh 8eh 0fh 8fh 10h 90h 11h 91h 12h 92h 13h 93h 14h 94h 15h 95h 16h 96h 17h 97h 18h 98h 1fh 9fh 20h a0h bfh c0h general purpose register note 1: not a physical register. 2: portd and porte are not available on the pic16c62/62a/r62. file address figure 4-7: pic16c63/r63/65/65a/r65 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 7fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch ffh bank 0 bank 1 indf (1) indf (1) tmr0 option pcl status fsr porta portb portd (2) porte (2) pclath intcon pcl status fsr trisa trisb trisd (2) trise (2) pclath intcon unimplemented data memory location; read as '0'. portc trisc pir1 pie1 pir2 pie2 tmr1l pcon tmr1h t1con tmr2 t2con pr2 sspbuf sspadd sspstat sspcon ccpr1l ccpr1h ccp1con ccpr2l ccpr2h ccp2con rcsta txreg rcreg txsta spbrg general purpose register general purpose register 0dh 8dh 0eh 8eh 0fh 8fh 10h 90h 11h 91h 12h 92h 13h 93h 14h 94h 15h 95h 16h 96h 17h 97h 18h 98h 19h 99h 1ah 9ah 1bh 9bh 1ch 9ch 1dh 9dh 1eh 9eh 1fh 9fh 20h a0h note 1: not a physical register 2: portd and porte are not available on the pic16c63/r63. file address
pic16c6x ds30234d-page 22 1997 microchip technology inc. figure 4-8: pic16c66/67 data memory map indirect addr. (*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspadd sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as '0'. * not a physical register. these registers are not implemented on the pic16c66. note: the upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in bank 0. this may require relocation of data memory usage in the user application code if upgrading to the pic16c66/67. file address indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 10ch 10dh 10eh 10fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11ah 11bh 11ch 11dh 11eh 11fh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 18ch 18dh 18eh 18fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19ah 19bh 19ch 19dh 19eh 19fh 120h 1a0h 17fh 1ffh bank 2 bank 3 indirect addr. (*) portd porte trisd trise tmr0 option pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con txsta spbrg general purpose register general purpose register general purpose register general purpose register 1efh 1f0h efh f0h 16fh 170h general purpose register general purpose register trisb portb 96 bytes 80 bytes 80 bytes 80 bytes 16 bytes 16 bytes (1) (1) (1) (1) accesses 70h-7fh in bank 0 accesses 70h-7fh in bank 0 accesses 70h-7fh in bank 0
1997 microchip technology inc. ds30234d-page 23 pic16c6x 4.2.2 special function registers: the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. the special function registers can be classi?d into two sets (core and peripheral). the registers associated with the ?ore functions are described in this section and those related to the operation of the peripheral fea- tures are described in the section of that peripheral fea- ture. table 4-1: special function registers for the pic16c61 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (1) status irp (4) rp1 (4) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read ---x xxxx ---u uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h unimplemented 08h unimplemented 09h unimplemented 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie t0ie inte rbie t0if intf rbif 0-00 000x 0-00 000u bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (1) status irp (4) rp1 (4) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register ---1 1111 ---1 1111 86h trisb portb data direction control register 1111 1111 1111 1111 87h unimplemented 88h unimplemented 89h unimplemented 8ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (1) intcon gie t0ie inte rbie t0if intf rbif 0-00 000x 0-00 000u legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'. shaded locations are unimplemented and read as ? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose con- tents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the irp and rp1 bits are reserved on the pic16c61, always maintain these bits clear.
pic16c6x ds30234d-page 24 1997 microchip technology inc. table 4-2: special function registers for the pic16c62/62a/r62 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (1) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx xxxx --uu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h unimplemented 09h unimplemented 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (6) (6) sspif ccp1if tmr2if tmr1if 00-- 0000 00-- 0000 0dh unimplemented 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h-1fh unimplemented legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the bor bit is reserved on the pic16c62, always maintain this bit set. 5: the irp and rp1 bits are reserved on the pic16c62/62a/r62, always maintain these bits clear. 6: pie1<7:6> and pir1<7:6> are reserved on the pic16c62/62a/r62, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 25 pic16c6x bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (1) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h unimplemented 89h unimplemented 8ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 (6) (6) sspie ccp1ie tmr2ie tmr1ie 00-- 0000 00-- 0000 8dh unimplemented 8eh pcon por bo r (4) ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 95h-9fh unimplemented table 4-2: special function registers for the pic16c62/62a/r62 (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the bor bit is reserved on the pic16c62, always maintain this bit set. 5: the irp and rp1 bits are reserved on the pic16c62/62a/r62, always maintain these bits clear. 6: pie1<7:6> and pir1<7:6> are reserved on the pic16c62/62a/r62, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 26 pic16c6x table 4-3: special function registers for the pic16c63/r63 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (1) status irp (4) rp1 (4) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx xxxx --uu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h unimplemented 09h unimplemented 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (5) (5) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh-1fh unimplemented legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the irp and rp1 bits are reserved on the pic16c63/r63, always maintain these bits clear. 5: pie1<7:6> and pir1<7:6> are reserved on the pic16c63/r63, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 27 pic16c6x bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (1) status irp (4) rp1 (4) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h unimplemented 89h unimplemented 8ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 (5) (5) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ccp2ie ---- ---0 ---- ---0 8eh pcon por bor ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h (2) txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h (2) spbrg baud rate generator register 0000 0000 0000 0000 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh unimplemented table 4-3: special function registers for the pic16c63/r63 (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the irp and rp1 bits are reserved on the pic16c63/r63, always maintain these bits clear. 5: pie1<7:6> and pir1<7:6> are reserved on the pic16c63/r63, always maintain these bits clear.
pic16c6x ds30234d-page 28 1997 microchip technology inc. table 4-4: special function registers for the pic16c64/64a/r64 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (1) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx xxxx --uu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h porte re2 re1 re0 ---- -xxx ---- -uuu 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (6) sspif ccp1if tmr2if tmr1if 00-- 0000 00-- 0000 0dh unimplemented 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h-1fh unimplemented legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the bor bit is reserved on the pic16c64, always maintain this bit set. 5: the irp and rp1 bits are reserved on the pic16c64/64a/r64, always maintain these bits clear. 6: pie1<6> and pir1<6> are reserved on the pic16c64/64a/r64, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 29 pic16c6x bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (1) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 8ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (6) sspie ccp1ie tmr2ie tmr1ie 00-- 0000 00-- 0000 8dh unimplemented 8eh pcon por bor (4) ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 95h-9fh unimplemented table 4-4: special function registers for the pic16c64/64a/r64 (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the bor bit is reserved on the pic16c64, always maintain this bit set. 5: the irp and rp1 bits are reserved on the pic16c64/64a/r64, always maintain these bits clear. 6: pie1<6> and pir1<6> are reserved on the pic16c64/64a/r64, always maintain these bits clear.
pic16c6x ds30234d-page 30 1997 microchip technology inc. table 4-5: special function registers for the pic16c65/65a/r65 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (1) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx xxxx --uu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h porte re2 re1 re0 ---- -xxx ---- -uuu 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (6) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh-1fh unimplemented legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the bor bit is reserved on the pic16c65, always maintain this bit set. 5: the irp and rp1 bits are reserved on the pic16c65/65a/r65, always maintain these bits clear. 6: pie1<6> and pir1<6> are reserved on the pic16c65/65a/r65, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 31 pic16c6x bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (1) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 8ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (6) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ccp2ie ---- ---0 ---- ---0 8eh pcon por bor (4) ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh unimplemented table 4-5: special function registers for the pic16c65/65a/r65 (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: the bor bit is reserved on the pic16c65, always maintain this bit set. 5: the irp and rp1 bits are reserved on the pic16c65/65a/r65, always maintain these bits clear. 6: pie1<6> and pir1<6> are reserved on the pic16c65/65a/r65, always maintain these bits clear.
pic16c6x ds30234d-page 32 1997 microchip technology inc. table 4-6: special function registers for the pic16c66/67 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (1) status irp rp1 rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx xxxx --uu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h (5) portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h (5) porte re2 re1 re0 ---- -xxx ---- -uuu 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (6) (4) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh-1fh unimplemented legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from any bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: pie1<6> and pir1<6> are reserved on the pic16c66/67, always maintain these bits clear. 5: portd, porte, trisd, and trise are not implemented on the pic16c66, read as '0'. 6: pspif (pir1<7>) and pspie (pie1<7>) are reserved on the pic16c66, maintain these bits clear.
1997 microchip technology inc. ds30234d-page 33 pic16c6x bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (1) status irp rp1 rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h (5) trisd portd data direction register 1111 1111 1111 1111 89h (5) trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 8ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (6) (4) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ccp2ie ---- ---0 ---- ---0 8eh pcon por bor ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh unimplemented table 4-6: special function registers for the pic16c66/67 (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from any bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: pie1<6> and pir1<6> are reserved on the pic16c66/67, always maintain these bits clear. 5: portd, porte, trisd, and trise are not implemented on the pic16c66, read as '0'. 6: pspif (pir1<7>) and pspie (pie1<7>) are reserved on the pic16c66, maintain these bits clear.
pic16c6x ds30234d-page 34 1997 microchip technology inc. bank 2 100h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 101h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 102h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 103h (1) status irp rp1 rp0 t o pd zdcc 0001 1xxx 000q quuu 104h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 105h unimplemented 106h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 107h unimplemented 108h unimplemented 109h unimplemented 10ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 10bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 10ch- 10fh unimplemented bank 3 180h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 183h (1) status irp rp1 rp0 t o pd zdcc 0001 1xxx 000q quuu 184h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 185h unimplemented 186h trisb portb data direction register 1111 1111 1111 1111 187h unimplemented 188h unimplemented 189h unimplemented 18ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 18bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 18ch- 19fh unimplemented table 4-6: special function registers for the pic16c66/67 (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from any bank. 2: the upper byte of the program counter (pc) is not directly accessible. pclath is a holding register for the pc whose contents are transferred to the upper byte of the program counter. (pc<12:8>) 3: other (non power-up) resets include external reset through mclr and the watchdog timer reset. 4: pie1<6> and pir1<6> are reserved on the pic16c66/67, always maintain these bits clear. 5: portd, porte, trisd, and trise are not implemented on the pic16c66, read as '0'. 6: pspif (pir1<7>) and pspie (pie1<7>) are reserved on the pic16c66, maintain these bits clear.
1997 microchip technology inc. ds30234d-page 35 pic16c6x 4.2.2.1 status register the status register, shown in figure 4-9, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the t o and p d bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see the ?nstruction set summary. note 1: for those devices that do not use bits irp and rp1 (status<7:6>), maintain these bits clear to ensure upward compatibility with future products. note 2: the c and dc bits operate as a borro w and digit borro w bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. figure 4-9: status register (address 03h, 83h, 103h, 183h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 t o pd z dc c r = readable bit w = writable bit - n = value at por reset x = unknown bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. bit 4: t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borro w bit (for addwf , addlw,sublw, and subwf instructions) (for borro w the polarity is reversed). 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borro w bit (for addwf , addlw,sublw, and subwf instructions)( for borro w the polarity is reversed). 1 = a carry-out from the most signi?ant bit of the result occurred 0 = no carry-out from the most signi?ant bit of the result note: a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c6x ds30234d-page 36 1997 microchip technology inc. 4.2.2.2 option register the option register is a readable and writable regis- ter which contains various control bits to con?ure the tmr0/wdt prescaler, the external int interrupt, tmr0, and the weak pull-ups on portb. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: to achieve a 1:1 prescaler assignment for tmr0 register, assign the prescaler to the watchdog timer. figure 4-10: option register (address 81h, 181h) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: rb p u : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
1997 microchip technology inc. ds30234d-page 37 pic16c6x 4.2.2.3 intcon register the intcon register is a readable and writable regis- ter which contains the various enable and ?g bits for the tmr0 register over?w, rb port change and exter- nal rb0/int pin interrupts. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). figure 4-11: intcon register (address 0bh, 8bh, 10bh 18bh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset x = unknown bit7 bit0 bit 7: gie: (1) global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie: (2) peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie: tmr0 over?w interrupt enable bit 1 = enables the tmr0 over?w interrupt 0 = disables the tmr0 over?w interrupt bit 4: inte: rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if: tmr0 over?w interrupt flag bit 1 = tmr0 register over?wed (must be cleared in software) 0 = tmr0 register did not over?w bit 1: intf: rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (see section 5.2 to clear the interrupt) 0 = none of the rb7:rb4 pins have changed state note 1: for the pic16c61/62/64/65, if an interrupt occurs while the gie bit is being cleared, the gie bit may unintentionally be re-enabled by the retfie instruction in the users interrupt service routine. refer to section 13.5 for a detailed description. 2: the peie bit (bit6) is unimplemented on the pic16c61, read as '0'. interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt ?g bits are clear prior to enabling an interrupt.
pic16c6x ds30234d-page 38 1997 microchip technology inc. 4.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. figure 4-12: pie1 register for pic16c62/62a/r62 (address 8ch) rw-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: reserved : always maintain these bits clear. bit 5-4: unimplemented : read as '0' bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt
1997 microchip technology inc. ds30234d-page 39 pic16c6x figure 4-13: pie1 register for pic16c63/r63/66 (address 8ch) figure 4-14: pie1 register for pic16c64/64a/r64 (address 8ch) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rcie txie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: reserved: always maintain these bits clear. bit 5: rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4: txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6: reserved : always maintain this bit clear. bit 5-4: unimplemented : read as '0' bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt
pic16c6x ds30234d-page 40 1997 microchip technology inc. figure 4-15: pie1 register for pic16c65/65a/r65/67 (address 8ch) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie rcie txie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6: reserved: always maintain this bit clear. bit 5: rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4: txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt
1997 microchip technology inc. ds30234d-page 41 pic16c6x 4.2.2.5 pir1 register this register contains the individual ?g bits for the peripheral interrupts. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt ?g bits are clear prior to enabling an interrupt. figure 4-16: pir1 register for pic16c62/62a/r62 (address 0ch) r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: reserved : always maintain these bits clear. bit 5-4: unimplemented : read as '0' bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?w occurred (must be cleared in software) 0 = no tmr1 register over?w occurred interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt ?g bits are clear prior to enabling an interrupt.
pic16c6x ds30234d-page 42 1997 microchip technology inc. figure 4-17: pir1 register for pic16c63/r63/66 (address 0ch) r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 rcif txif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: reserved: always maintain these bits clear. bit 5: rcif: usart receive interrupt flag bit 1 = the usart receive buffer is full (cleared by reading rcreg) 0 = the usart receive buffer is empty bit 4: txif: usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (cleared by writing to txreg) 0 = the usart transmit buffer is full bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?w occurred (must be cleared in software) 0 = no tmr1 register over?w occurred interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt ?g bits are clear prior to enabling an interrupt.
1997 microchip technology inc. ds30234d-page 43 pic16c6x figure 4-18: pir1 register for pic16c64/64a/r64 (address 0ch) r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspif: parallel slave port interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write operation has taken place bit 6: reserved : always maintain this bit clear. bit 5-4: unimplemented : read as '0' bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?w occurred (must be cleared in software) 0 = no tmr1 register occurred interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt ?g bits are clear prior to enabling an interrupt.
pic16c6x ds30234d-page 44 1997 microchip technology inc. figure 4-19: pir1 register for pic16c65/65a/r65/67 (address 0ch) r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif rcif txif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspif: parallel slave port interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write operation has taken place bit 6: reserved: always maintain this bit clear. bit 5: rcif: usart receive interrupt flag bit 1 = the usart receive buffer is full (cleared by reading rcreg) 0 = the usart receive buffer is empty bit 4: txif: usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (cleared by writing to txreg) 0 = the usart transmit buffer is full bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?w occurred (must be cleared in software) 0 = no tmr1 register over?w occurred interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt ?g bits are clear prior to enabling an interrupt.
1997 microchip technology inc. ds30234d-page 45 pic16c6x 4.2.2.6 pie2 register this register contains the ccp2 interrupt enable bit. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 4-20: pie2 register (address 8dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ccp2ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt
pic16c6x ds30234d-page 46 1997 microchip technology inc. 4.2.2.7 pir2 register this register contains the ccp2 interrupt flag bit. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 . note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt ?g bits are clear prior to enabling an interrupt. figure 4-21: pir2 register (address 0dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ccp2if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2if : ccp2 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt ?g bits are clear prior to enabling an interrupt.
1997 microchip technology inc. ds30234d-page 47 pic16c6x 4.2.2.8 pcon register the power control register (pcon) contains a ?g bit to allow differentiation between a power-on reset to an external mclr reset or wdt reset. those devices with brown-out detection circuitry contain an additional bit to differentiate a brown-out reset condition from a power-on reset condition. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a ?on't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the con?uration word). figure 4-22: pcon register for pic16c62/64/65 (address 8eh) figure 4-23: pcon register for pic16c62a/r62/63/r63/64a/r64/65a/r65/66/67 (address 8eh) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-q por r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset q = value depends on conditions bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: reserved this bit should be set upon a power-on reset by user software and maintained as set. use of this bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-q por bor r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset q = value depends on conditions bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: po r : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: b or : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16c6x ds30234d-page 48 1997 microchip technology inc. 4.3 p cl and p cla th the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the upper bits (pc<12:8>) are not readable, but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 4-24 shows the two situations for the loading of the pc. the upper example in the ?ure shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower example in the ?- ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 4-24: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 word block). refer to the application note ?mplementing a table read (an556). 4.3.2 stack the pic16cxx family has an 8 deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or a pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the ?st push. the tenth push overwrites the second push (and so on). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 pc 12 8 7 0 5 pclath<4:0> pclath instr uction with pcl as alu goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl destination 4.4 pr ogram memor y p a ging pic16c6x devices are capable of addressing a contin- uous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction the upper two bits of the address are provided by pclath<4:3>. when doing a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is exe- cuted, the entire 13-bit pc is pushed onto the stack. therefore, manipulation of the pclath<4:3> bits are not required for the return instructions (which pops the address from the stack). note 1: there are no status bits to indicate stack over?ws or stack under?w conditions. note 2: there are no instructions mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw, and retfie instruc- tions, or the vectoring to an interrupt address applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: pic16c6x devices with 4k or less of pro- gram memory ignore paging bit pclath<4>. the use of pclath<4> as a general purpose read/write bit is not rec- ommended since this may affect upward compatibility with future products.
1997 microchip technology inc. ds30234d-page 49 pic16c6x example 4-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that the pclath is saved and restored by the interrupt service routine (if interrupts are used). example 4-1: call of a subroutine in page 1 from page 0 org 0x500 bsf pclath,3 ;select page 1 (800h-fffh) bcf pclath,4 ;only on >4k devices call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : : org 0x900 sub1_p1: ;called subroutine : ;page 1 (800h-fffh) : return ;return to call subroutine ;in page 0 (000h-7ffh) 4.5 indirect ad dressing, indf and f sr register s the indf register is not a physical register. address- ing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself indirectly (fsr = '0') will produce 00h. writing to the indf regis- ter indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 4-25. a simple program to clear ram location 20h-2fh using indirect addressing is shown in example 4-2. example 4-2: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 4-25: direct/indirect addressing for memory map detail see figure 4-5, figure 4-6, figure 4-7, and figure 4-8. bank select bank select location select location select direct addressing indirect addressing rp1: rp0 6 0 from opcode irp 7 fsr 0 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h data memory 7fh 00h 17fh 100h 1ffh 180h
pic16c6x ds30234d-page 50 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30234d-page 51 pic16c6x 5.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function(s) for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. 5.1 por t a and trisa register all devices have a 6-bit wide porta, except for the pic16c61 which has a 5-bit wide porta. pin ra4/t0cki is a schmitt trigger input and an open drain output. all other ra port pins have ttl input lev- els and full cmos output drivers. all pins have data direction bits (tris registers) which can con?ure these pins as output or input. setting a bit in the trisa register puts the correspond- ing output driver in a hi-impedance mode. clearing a bit in the trisa register puts the contents of the output latch on the selected pin. reading porta register reads the status of the pins whereas writing to it will write to the port latch. all write operations are read-modify-write operations. there- fore, a write to a port implies that the port pins are read, this value is modi?d, and then written to the port data latch. pin ra4 is multiplexed with timer0 module clock input to become the ra4/t0cki pin. example 5-1: initializing porta bcf status, rp0 ; bcf status, rp1 ; pic16c66/67 only clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as '0'. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 5-1: block diagram of the ra3:ra0 pins and the ra5 pin figure 5-2: block diagram of the ra4/t0cki pin data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port ttl input buffer v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . 2: the pic16c61 does not have an ra5 pin. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input note 1: i/o pin has protection diodes to v ss only. q d q ck q d q ck en qd en
pic16c6x ds30234d-page 52 1997 microchip technology inc. table 5-1: porta functions table 5-2: registers/bits associated with porta name bit# buffer type function ra0 bit0 ttl input/output ra1 bit1 ttl input/output ra2 bit2 ttl input/output ra3 bit3 ttl input/output ra4/t0cki bit4 st input/output or external clock input for timer0. output is open drain type. ra5/ss (1) bit5 ttl input/output or slave select input for synchronous serial port. legend: ttl = ttl input, st = schmitt trigger input note 1: the pic16c61 does not have porta<5> or trisa<5>, read as ?? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ra5 (1) ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 85h trisa porta data direction register (1) --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note 1: porta<5> and trisa<5> are not implemented on the pic16c61, read as '0'.
1997 microchip technology inc. ds30234d-page 53 pic16c6x 5.2 p or tb and t risb register portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a bit in the trisb register puts the corresponding output driver in a hi-impedance mode. clearing a bit in the trisb register puts the contents of the output latch on the selected pin(s). example 5-2: initializing portb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit r bpu (option<7>). the weak pull-up is automatically turned off when the port pin is con?ured as an output. the pull-ups are also disabled on a power-on reset. four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin con?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?ismatch outputs of rb7:rb4 are or?d together to generate the rb port change interrupt with ?g bit rbif (intcon<0>). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear ?g bit rbif. a mismatch condition will continue to set ?g bit rbif. reading portb will end the mismatch condition, and allow ?g bit rbif to be cleared. this interrupt on mismatch feature, together with soft- ware con?urable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. refer to the embedded control handbook, application note, ?mplementing wake-up on key stroke (an552) . the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 5-3: block diagram of the rb7:rb4 pins for pic16c61/62/64/65 note: for pic16c61/62/64/65, if a change on the i/o pin should occur when a read operation is being executed (start of the q2 cycle), then interrupt ?g bit rbif may not get set. data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rpb u bit (option<7>). st buffer rb7:rb6 in serial programming mode
pic16c6x ds30234d-page 54 1997 microchip technology inc. figure 5-4: block diagram of the rb7:rb4 pins for pic16c62a/63/r63/64a/65a/ r65/66/67 data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . st buffer rb7:rb6 in serial programming mode q3 q1 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rpb u bit (option<7>). figure 5-5: block diagram of the rb3:rb0 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rpb u bit (option<7>). table 5-3: portb functions table 5-4: summary of registers associated with portb name bit# buffer type function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
1997 microchip technology inc. ds30234d-page 55 pic16c6x 5.3 p or tc and t risc register portc is an 8-bit wide bi-directional port. each pin is individually con?urable as an input or output through the trisc register. portc is multiplexed with several peripheral functions (table 5-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in de?ing tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. example 5-3: initializing portc bcf status, rp0 ; bcf status, rp1 ; pic16c66/67 only clrf portc ; initialize portc by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 5-6: portc block diagram port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en p er ipher al data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. table 5-5: portc functions for pic16c62/64 name bit# buffer type function rc0/t1osi/t1cki bit0 st input/output port pin or timer1 oscillator input or timer1 clock input rc1/t1oso bit1 st input/output port pin or timer1 oscillator output rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output rc6 bit6 st input/output port pin rc7 bit7 st input/output port pin legend: st = schmitt trigger input
pic16c6x ds30234d-page 56 1997 microchip technology inc. table 5-6: portc functions for pic16c62a/r62/64a/r64 table 5-7: portc functions for pic16c63/r63/65/65a/r65/66/67 table 5-8: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output or timer1 clock input rc1/t1osi bit1 st input/output port pin or timer1 oscillator input rc2/ccp1 bit2 st input/output port pin or capture input/compare output/pwm1 output rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output rc6 bit6 st input/output port pin rc7 bit7 st input/output port pin legend: st = schmitt trigger input name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output or timer1 clock input rc1/t1osi/ccp2 bit1 st input/output port pin or timer1 oscillator input or capture2 input/compare2 output/pwm2 output rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output rc6/tx/ck bit6 st input/output port pin or usart asynchronous transmit, or usart syn- chronous clock rc7/rx/dt bit7 st input/output port pin or usart asynchronous receive, or usart syn- chronous data legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged.
1997 microchip technology inc. ds30234d-page 57 pic16c6x 5.4 p or td and t risd register portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually con?urable as input or out- put. portd can be con?ured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 5-7: portd block diagram (in i/o port mode) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en table 5-9: portd functions table 5-10: summary of registers associated with portd name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0 rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1 rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2 rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3 rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4 rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5 rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6 rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7 legend: st = schmitt trigger input, ttl = ttl input note 1: buffer is a schmitt trigger when in i/o mode, and a ttl buffer when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by portd.
pic16c6x ds30234d-page 58 1997 microchip technology inc. 5.5 p or te and t rise register porte has three pins, re2/cs , re1/wr , and re0/rd which are individually con?urable as inputs or outputs. these pins have schmitt trigger input buff- ers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are con?ured as digital inputs). in this mode the input buffers are ttl. figure 5-9 shows the trise register, which controls the parallel slave port operation and also controls the direction of the porte pins. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 5-8: porte block diagram (in i/o port mode) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . figure 5-9: trise register (address 89h) r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode bit2 bit1 bit0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7 : ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6: obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5: ibov : input buffer over?w detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no over?w occurred bit 4: pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3: unimplemented : read as '0' porte data direction bits bit 2: bit2 : direction control bit for pin re2/cs 1 = input 0 = output bit 1: bit1 : direction control bit for pin re1/wr 1 = input 0 = output bit 0: bit0 : direction control bit for pin re0/rd 1 = input 0 = output
1997 microchip technology inc. ds30234d-page 59 pic16c6x table 5-11: porte functions table 5-12: summary of registers associated with porte name bit# buffer type function re0/rd bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode. rd 1 = not a read operation 0 = read operation. the system reads the portd register (if chip selected) re1/wr bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode. wr 1 = not a write operation 0 = write operation. the system writes to the portd register (if chip selected) re2/cs bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode. cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input, ttl = ttl input note 1: buffer is a schmitt trigger when in i/o mode, and a ttl buffer when in parallel slave port (psp) mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells not used by porte.
pic16c6x ds30234d-page 60 1997 microchip technology inc. 5.6 i /o pr ogramming considerations 5.6.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs de?ed. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (e.g., bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. reading the port register, reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (ex. bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. example 5-4 shows the effect of two sequential read-modify-write instructions on an i/o port. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 example 5-4: read-modify-write instructions on an i/o port ;initial port settings: portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- --------- bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bsf status, rp0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp ; ;note that the user may have expected the ;pin values to be 00pp pppp. the 2nd bcf ;caused rb7 to be latched as the pin value ;(high). a pin actively outputting a low or high should not be driven from external devices at the same time in order to change the level on this pin (?ired-or? ?ired-and?. the resulting high output currents may damage the chip. 5.6.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-10). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow the pin voltage to stabilize (load depen- dent) before the next instruction which causes that ?e to be read into the cpu is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-10: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb write to portb nop port pin sampled here nop movf portb,w instruction executed movwf portb write to portb nop movf portb,w pc t pd note: this example shows a write to portb followed by a read from portb. note that: data setup time = (0.25t cy - t pd ) where t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be prob- lematic.
1997 microchip technology inc. ds30234d-page 61 pic16c6x 5.7 p arallel sla ve p or t portd operates as an 8-bit wide parallel slave port (microprocessor port) when control bit pspmode (trise<4>) is set. in slave mode it is asynchronously readable and writable by the external world through r d control input (re0/rd ) and w r control input pin (re1/wr ). it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the c s (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be con?ured as inputs (set). there are actually two 8-bit latches, one for data-out (from the pic16/17) and one for data input. the user writes 8-bit data to portd data latch and reads data from the port pin latch (note that they have the same address). in this mode, the trisd register is ignored since the microprocessor is controlling the direction of data ?w. a write to the psp occurs when both the cs and wr lines are ?st detected low. when either the cs or wr lines become high (level triggered), then the input buffer full status ?g bit ibf (trise<7>) is set on the q4 clock cycle, following the next q2 cycle, to signal the write is complete (figure 5-12). the interrupt ?g bit pspif (pir1<7>) is also set on the same q4 clock cycle. ibf can only be cleared by reading the portd input latch. the input buffer over?w status ?g bit ibov (trise<5>) is set if a second write to the parallel slave port is attempted when the previous byte has not been read out of the buffer. a read from the psp occurs when both the cs and rd lines are ?st detected low. the output buffer full sta- tus ?g bit obf (trise<6>) is cleared immediately (figure 5-13) indicating that the portd latch is waiting to be read by the external bus. when either the cs or rd pin becomes high (level triggered), the interrupt ?g bit pspif is set on the q4 clock cycle, following the next q2 cycle, indicating that the read is complete. obf remains low until data is written to portd by the user ?mware. when not in parallel slave port mode, the ibf and obf bits are held clear. however, if ?g bit ibov was previ- ously set, it must be cleared in ?mware. an interrupt is generated and latched into ?g bit pspif when a read or write operation is completed. pspif must be cleared by the user in ?mware and the interrupt can be disabled by clearing the interrupt enable bit pspie (pie1<7>). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 5-11: portd and porte as a parallel slave port data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt ?g pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl
pic16c6x ds30234d-page 62 1997 microchip technology inc. figure 5-12: parallel slave port write waveforms figure 5-13: parallel slave port read waveforms table 5-13: registers associated with parallel slave port address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd psp7 psp6 psp5 psp4 psp3 psp2 psp1 psp0 xxxx xxxx uuuu uuuu 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif (1) rcif (2) txif (2) sspif ccp1if tmr2if trm1if 0000 0000 0000 0000 8ch pie1 pspie (1) rcie (2) txie (2) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by the psp. note 1: these bits are reserved, always maintain these bits clear. 2: these bits are implemented on the pic16c65/65a/r65/67 only. q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0>
1997 microchip technology inc. ds30234d-page 63 pic16c6x 6.0 overview of timer modules all pic16c6x devices have three timer modules except for the pic16c61, which has one timer module. each module can generate an interrupt to indicate that an event has occurred (i.e., timer over?w). each of these modules are detailed in the following sections. the timer modules are: timer0 module (section 7.0) timer1 module (section 8.0) timer2 module (section 9.0) 6.1 t imer0 o ver vie w the timer0 module is a simple 8-bit over?w counter. the clock source can be either the internal system clock (fosc/4) or an external clock. when the clock source is an external clock, the timer0 module can be selected to increment on either the rising or falling edge. the timer0 module also has a programmable pres- caler option. this prescaler can be assigned to either the timer0 module or the watchdog timer. bit psa (option<3>) assigns the prescaler, and bits ps2:ps0 (option<2:0>) determine the prescaler value. tmr0 can increment at the following rates: 1:1 when the pres- caler is assigned to watchdog timer, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256. synchronization of the external clock occurs after the prescaler. when the prescaler is used, the external clock frequency may be higher then the devices fre- quency. the maximum frequency is 50 mhz, given the high and low time requirements of the clock. 6.2 timer1 o ver vie w timer1 is a 16-bit timer/counter. the clock source can be either the internal system clock (fosc/4), an external clock, or an external crystal. timer1 can operate as either a timer or a counter. when operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. asynchronous operation allows timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power sav- ings of sleep mode. timer1 also has a prescaler option which allows tmr1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. tmr1 can be used in conjunction with the capture/ compare/pwm module. when used with a ccp mod- ule, timer1 is the time-base for 16-bit capture or 16-bit compare and must be synchronized to the device. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 6.3 timer2 o ver vie w timer2 is an 8-bit timer with a programmable prescaler and a programmable postscaler, as well as an 8-bit period register (pr2). timer2 can be used with the ccp module (in pwm mode) as well as the baud rate generator for the synchronous serial port (ssp). the prescaler option allows timer2 to increment at the fol- lowing rates: 1:1, 1:4, and 1:16. the postscaler allows tmr2 register to match the period register (pr2) a programmable number of times before generating an interrupt. the postscaler can be programmed from 1:1 to 1:16 (inclusive). 6.4 ccp o ver vie w the ccp module(s) can operate in one of three modes: 16-bit capture, 16-bit compare, or up to 10-bit pulse width modulation (pwm). capture mode captures the 16-bit value of tmr1 into the ccprxh:ccprxl register pair. the capture event can be programmed for either the falling edge, rising edge, fourth rising edge, or sixteenth rising edge of the ccpx pin. compare mode compares the tmr1h:tmr1l register pair to the ccprxh:ccprxl register pair. when a match occurs, an interrupt can be generated and the output pin ccpx can be forced to a given state (high or low) and timer1 can be reset. this depends on control bits ccpxm3:ccpxm0. pwm mode compares the tmr2 register to a 10-bit duty cycle register (ccprxh:ccprxl<5:4>) as well as to an 8-bit period register (pr2). when the tmr2 reg- ister = duty cycle register, the ccpx pin will be forced low. when tmr2 = pr2, tmr2 is cleared to 00h, an interrupt can be generated, and the ccpx pin (if an out- put) will be forced high. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 64 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30234d-page 65 pic16c6x 7.0 timer0 module the timer0 module has the following features: 8-bit timer/counter register, tmr0 - read and write capability - interrupt on over?w from ffh to 00h 8-bit software programmable prescaler internal or external clock select - edge select for external clock figure 7-1 is a simpli?d block diagram of the timer0 module. timer mode is selected by clearing bit t0cs (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two instruction cycles (figure 7-2 and figure 7-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs. in this mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the source edge select bit t0se applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 (option<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are dis- cussed in detail in section 7.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the pres- caler assignment is controlled in software by control bit psa (option<3>). clearing bit psa will assign the prescaler to the timer0 module. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. section 7.3 details the operation of the prescaler. 7.1 t mr0 i nterrupt the tmr0 interrupt is generated when the register (tmr0) over?ws from ffh to 00h. this over?w sets interrupt ?g bit t0if (intcon<2>). the interrupt can be masked by clearing enable bit t0ie (intcon<5>). flag bit t0if must be cleared in software by the timer0 interrupt service routine before re-enabling this inter- rupt. the tmr0 interrupt cannot wake the processor from sleep since the timer is shut off during sleep. figure 7-4 displays the timer0 interrupt timing. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 7-1: timer0 block diagram figure 7-2: timer0 timing: internal clock/no prescaler note 1: bits, t0cs, t0se, psa, and ps2, ps1, ps0 are (option<5:0). 2: the prescaler is shared with watchdog timer (refer to figure 7-6 for detailed diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 reg psout (2 cycle delay) psout data bus 8 set bit t0if on over?w psa ps2, ps1, ps0 3 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed
pic16c6x ds30234d-page 66 1997 microchip technology inc. figure 7-3: timer0 timing: internal clock/prescale 1:2 figure 7-4: tmr0 interrupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout (3) timer0 t0if bit (intcon<2>) feh gie bit (intcon<7>) instr uction pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h note 1: interrupt ?g bit t0if is sampled here (every q1). 2: interrupt latency = 4tcy where tcy = instruction cycle time. 3: clkout is available only in rc oscillator mode. f lo w
1997 microchip technology inc. ds30234d-page 67 pic16c6x 7.2 using timer0 with external cloc k when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 7.2.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 7-5). therefore, it is necessary for t0cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to the electrical speci?ation of the desired device. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 when a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- caler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. there- fore, it is necessary for t0cki to have a period of at least 4tosc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. refer to param- eters 40, 41 and 42 in the electrical speci?ation of the desired device. 7.2.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 7-5 shows the delay from the external clock edge to the timer incrementing. figure 7-5: timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 note 1: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. (3) (1) small pulse misses sampling
pic16c6x ds30234d-page 68 1997 microchip technology inc. 7.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (figure 7-6). for simplicity, this counter is being referred to as ?rescaler through- out this data sheet. note that the prescaler may be used by either the timer0 module or the watchdog timer, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf tmr0, movwf tmr0, bsf tmr0,bitx ) will clear the pres- caler count. when assigned to the watchdog timer, a clrwdt instruction will clear the watchdog timer and the prescaler count. the prescaler is not readable or writable. note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. figure 7-6: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set ?g bit t0if on over?w 8 psa t0cs
1997 microchip technology inc. ds30234d-page 69 pic16c6x 7.3.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed ?n the ? during program execution. example 7-1: changing prescaler (timer0 ? wdt) to change prescaler from the wdt to the timer0 mod- ule, use the sequence shown in example 7-2. example 7-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and prescaler bsf status, rp0 ;bank 1 movlw b'xxxx0xxx' ;select tmr0, new prescale value and clock source movwf option_reg ; bcf status, rp0 ;bank 0 table 7-1: registers associated with timer0 note: to avoid an unintended device reset, the following instruction sequence (shown in example 7-1) must be executed when changing the prescaler assignment from timer0 to the wdt. this precaution must be followed even if the wdt is disabled. 1) bsf status, rp0 ;bank 1 lines 2 and 3 do not have to be included if the ?al desired prescale value is other than 1:1. if 1:1 is ?al desired value, then a temporary prescale value is set in lines 2 and 3 and the ?al prescale value will be set in lines 10 and 11. 2) movlw b'xx0x0xxx' ;select clock source and prescale value of 3) movwf option_reg ;other than 1:1 4) bcf status, rp0 ;bank 0 5) clrf tmr0 ;clear tmr0 and prescaler 6) bsf status, rp1 ;bank 1 7) movlw b'xxxx1xxx' ;select wdt, do not change prescale value 8) movwf option_reg ; 9) clrwdt ;clears wdt and prescaler 10) movlw b'xxxx1xxx' ;select new prescale value and wdt 11) movwf option_reg ; 12) bcf status, rp0 ;bank 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h, 101h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie (1) t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h, 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa porta data direction register (1) --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. note 1: trisa<5> and bit peie are not implemented on the pic16c61, read as '0'.
pic16c6x ds30234d-page 70 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30234d-page 71 pic16c6x 8.0 timer1 module timer1 is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l) which are readable and writable. register tmr1 (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on over?w which is latched in interrupt ?g bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clear- ing the tmr1 interrupt enable bit tmr1ie (pie1<0>). timer1 can operate in one of two modes: as a timer as a counter the operating mode is determined by clock select bit, tmr1cs (t1con<1>) (figure 8-2). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 timer1 also has an internal ?eset input? this reset can be generated by ccp1 or ccp2 (capture/compare/ pwm) module. see section 10.0 for details. figure 8-1 shows the timer1 control register. for the pic16c62a/r62/63/r63/64a/r64/65a/r65/ r66/67, when the timer1 oscillator is enabled (t1oscen is set), the rc1 and rc0 pins become inputs. that is, the trisc<1:0> value is ignored. for the pic16c62/64/65, when the timer1 oscillator is enabled (t1oscen is set), rc1 pin becomes an input, however the rc0 pin will have to be con?ured as an input by setting the trisc<0> bit. the timer1 module also has a software programmable prescaler. figure 8-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented : read as '0' bit 5-4: t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off note: the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2: t1s ync : timer1 external clock input synchronization control bit tmr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from t1osi (on the rising edge) (see pinouts for pin with t1osi function) 0 = internal clock (fosc/4) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1
pic16c6x ds30234d-page 72 1997 microchip technology inc. 8.1 timer1 operation in timer mode timer mode is selected by clearing bit tmr1cs (t1con<1>). in this mode, the input clock to the timer is fosc/4. the synchronize control bit t1 s ync (t1con<2>) has no effect since the internal clock is always in sync. 8.2 timer1 operation in sync hr oniz ed counter mode counter mode is selected by setting bit tmr1cs. in this mode the timer increments on every rising edge of clock input on t1osi when enable bit t1oscen is set or pin with t1cki when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the pres- caler stage is an asynchronous ripple counter. in this con?uration, during sleep mode, timer1 will not increment even if an external clock is present, since the synchronization circuit is shut off. the prescaler, however, will continue to increment. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: the t1osi function is multiplexed to differ- ent pins, depending on the device. see the pinout descriptions to see which pin has the t1osi function. 8.2.1 external clock input timing for synchronized counter mode when an external clock input is used for timer1 in syn- chronized counter mode, it must meet certain require- ments. the external clock requirement is due to internal phase clock (tosc) synchronization. also, there is a delay in the actual incrementing of tmr1 after syn- chronization. when the prescaler is 1:1, the external clock input is the same as the prescaler output. the synchronization of t1cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t1cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to appropriate electrical speci?ation section, parameters 45, 46, and 47. when a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripple- counter type prescaler so that the prescaler output is symmetrical. in order for the external clock to meet the sampling requirement, the ripple counter must be taken into account. therefore, it is necessary for t1cki to have a period of at least 4tosc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t1cki high and low time is that they do not violate the minimum pulse width requirements of 10 ns). refer to applicable electrical speci?ation sec- tion, parameters 40, 42, 45, 46, and 47. figure 8-2: timer1 block diagram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) tmr1if over?w interrupt fosc/4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso (2) t1osi (2) tmr1 ?g bit (3) note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. 2: see pinouts for pins with t1oso and t1osi functions. 3: for the pic16c62/64/65, the schmitt trigger is not implemented in external clock mode.
1997 microchip technology inc. ds30234d-page 73 pic16c6x 8.3 timer1 operation in async hr onous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and gener- ate an interrupt on over?w which will wake the proces- sor. however, special precautions in software are needed to read-from or write-to the timer1 register pair, tmr1l and tmr1h (section 8.3.2). in asynchronous counter mode, timer1 cannot be used as a time-base for capture or compare operations. 8.3.1 external clock input timing with unsynchronized clock if control bit t1sync is set, the timer will increment completely asynchronously. the input clock must meet certain minimum high time and low time requirements, as speci?d in timing parameters (45 - 47). 8.3.2 reading and writing tmr1 in asynchronous counter mode reading tmr1h or tmr1l, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may over?w between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers while the register is incrementing. this may produce an unpre- dictable value in the timer register. reading the 16-bit value requires some care. example 8-1 is an example routine to read the 16-bit timer value. this is useful if the timer cannot be stopped. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 example 8-1: reading a 16-bit free-running timer ; all interrupts are disabled movf tmr1h, w ;read high byte movwf tmph ; movf tmr1l, w ;read low byte movwf tmpl ; movf tmr1h, w ;read high byte subwf tmph, w ;sub 1st read ;with 2nd read btfsc status,z ;is result = 0 goto continue ;good 16-bit read ; tmr1l may have rolled over between the read ; of the high and low bytes. reading the high ; and low bytes now will read a good value. movf tmr1h, w ;read high byte movwf tmph ; movf tmr1l, w ;read low byte movwf tmpl ; ; re-enable interrupt (if required) continue ;continue with : ;your code 8.4 t imer1 oscillator a crystal oscillator circuit is built in-between pins t1osi (input) and t1oso (ampli?r output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 8-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must allow a software time delay to ensure proper oscillator start-up. table 8-1: capacitor selection for the timer1 oscillator applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components.
pic16c6x ds30234d-page 74 1997 microchip technology inc. 8.5 r esetting timer1 using a ccp t rig g er output ccp2 is implemented on the pic16c63/r63/65/65a/ r65/66/67 only. if ccp1 or ccp2 module is con?ured in compare mode to generate a ?pecial event trigger (ccpxm3:ccpxm0 = 1011 ), this signal will reset timer1. timer1 must be con?ured for either timer or synchro- nized counter mode to take advantage of this feature. if the timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1 or ccp2, the write will take precedence. in this mode of operation, the ccprxh:ccprxl regis- ters pair effectively becomes the period register for the timer1 module. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: the ?pecial event trigger from the ccp1and ccp2 modules will not set inter- rupt ?g bit tmr1if(pir1<0>). 8.6 r esetting of tmr1 r egister p air (tmr1h : tmr1l) the tmr1h and tmr1l registers are not reset to 00h on a por or any other reset except by the ccp1 or ccp2 special event trigger. the t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescaler. in all other resets, the reg- ister is unaffected. 8.7 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 table 8-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (2) (3) rcif (1) txif (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (2) (3) rcie (1) txie (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1 s ync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: the usart is implemented on the pic16c63/r63/65/65a/r65/66/67 only. 2: bits pspie and pspif are reserved on the pic16c62/62a/r62/63/r63/66, always maintain these bits clear. 3: pir1<6> and pie1<6> are reserved, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 75 pic16c6x 9.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it is especially suitable as pwm time-base for pwm mode of ccp module(s). tmr2 is a readable and writable register, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is ini- tialized to ffh upon reset. the match output of the tmr2 register goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling, inclusive) to generate a tmr2 interrupt (latched in ?g bit tmr2if (pir1<1>)). the timer2 module can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power con- sumption. figure 9-2 shows the timer2 control register. t2con is cleared upon reset which initializes timer2 as shut off with the prescaler and postscaler at a 1:1 value. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 9.1 timer2 prescaler and p ostscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (por, bor, m clr reset, or wdt reset). tmr2 is not cleared when t2con is written. 9.2 o utput of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate shift clock. figure 9-1: timer2 block diagram applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 comparator tmr2 sets interrupt tmr2if tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 fosc/4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 tmr2 ?g bit, note 1: tmr2 register output can be software selected by the ssp module as a baud clock. figure 9-2: t2con: timer2 control register (address 12h) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: unimplemented : read as '0' bit 6-3: toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = 1:1 prescale 01 = 1:4 prescale 1x = 1:16 prescale
pic16c6x ds30234d-page 76 1997 microchip technology inc. table 9-1: registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (2) (3) rcif (1) txif (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (2) (3) rcie (1) txie (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer2. note 1: the usart is implemented on the pic16c63/r63/65/65a/r65/66/67 only. 2: bits pspie and pspif are reserved on the pic16c62/62a/r62/63/r63/66, always maintain these bits clear. 3: pir1<6> and pie1<6> are reserved, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 77 pic16c6x 10.0 capture/compare/pwm (ccp) module(s) each ccp (capture/compare/pwm) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register, or as a pwm master/slave duty cycle register. both the ccp1 and ccp2 modules are identical in operation, with the exception of the operation of the special event trigger. table 10-1 and table 10-2 show the resources and interactions of the ccp modules(s). in the following sections, the operation of a ccp module is described with respect to ccp1. ccp2 operates the same as ccp1, except where noted. ccp1 module: capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ccp1 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ccp2 ccp2 module: capture/compare/pwm register2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. all are readable and writable. for use of the ccp modules, refer to the embedded control handbook, ?sing the ccp modules (an594). table 10-1: ccp mode - timer resource ccp mode timer resource capture compare pwm timer1 timer1 timer2 table 10-2: interaction of two ccp modules ccpx mode ccpy mode interaction capture capture same tmr1 time-base. capture compare the compare should be con?ured for the special event trigger, which clears tmr1. compare compare the compare(s) should be con?ured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency, and update rate (tmr2 interrupt). pwm capture none pwm compare none
pic16c6x ds30234d-page 78 1997 microchip technology inc. figure 10-1: ccp1con register (address 17h) / ccp2con register (address 1dh) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: ccpxx:ccpxy : pwm least signi?ant bits capture mode unused compare mode unused pwm mode these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0: ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (bit ccpxif is set) 1001 = compare mode, clear output on match (bit ccpxif is set) 1010 = compare mode, generate software interrupt on match (bit ccpxif is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set; ccp1 resets tmr1; ccp2 resets tmr1) 11xx = pwm mode 10.1 captur e mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1 (figure 10-2). an event is de?ed as: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request ?g bit ccp1if (pir1<2>) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 10.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be con?- ured as an input by setting the trisc<2> bit. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: if the rc2/ccp1 pin is con?ured as an output, a write to portc can cause a cap- ture condition. figure 10-2: capture mode operation block diagram 10.1.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work consistently. 10.1.3 software interrupt when the capture event is changed, a false capture interrupt may be generated. the user should clear enable bit ccp1ie (pie1<2>) to avoid false interrupts and should clear ?g bit ccp1if following any such change in operating mode. ccpr1h ccpr1l tmr1h tmr1l set ccp1if pir1<2> capture enable qs ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin
1997 microchip technology inc. ds30234d-page 79 pic16c6x 10.1.4 ccp prescaler there are four prescaler settings, speci?d by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore the ?st capture may be from a non-zero prescaler. example 10-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ?alse interrupt. example 10-1: changing between capture prescalers clrf ccp1con ; turn ccp module off movlw new_capt_ps ; load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ; load ccp1con with ; this value 10.2 c om pare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time interrupt ?g bit ccp1if is set. figure 10-3: compare mode operation block diagram applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger will reset timer1, but not special event trigger set ccp1if pir1<2> match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable set interrupt ?g bit tmr1if (pir1<0>). 10.2.1 ccp pin configuration the user must con?ure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 10.2.1 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 10.2.2 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is gen- erated (if enabled). 10.2.3 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 and ccp2 resets the tmr1 register pair. this allows the ccpr1h:ccpr1l and ccpr2h:ccpr2l registers to effectively be 16-bit programmable period register(s) for timer1. for compatibility issues, the special event trigger out- put of ccp1 (p i c16c72 ) and ccp2 (all other p ic16c7x devices) also starts an a/d conversion. note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the ?pecial event trigger from the ccp1and ccp2 modules will not set inter- rupt ?g bit tmr1if (pir1<0>).
pic16c6x ds30234d-page 80 1997 microchip technology inc. 10.3 p wm m ode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 10-4 shows a simpli?d block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see section 10.3.3. figure 10-4: simplified pwm block diagram a pwm output (figure 10-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 10-5: pwm output applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc2 rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 10.3.1 pwm period the pwm period is speci?d by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] 4 t osc (tmr2 prescale value) pwm frequency is de?ed as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the pwm duty cycle is latched from ccpr1l into ccpr1h the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) 10.3.2 pwm duty cycle the pwm duty cycle is speci?d by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available: the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) tosc (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: note: the timer2 postscaler (see section 9.1) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period the ccp1 pin will not be forced to the low level. log ( f pwm log(2) f osc ) bits =
1997 microchip technology inc. ds30234d-page 81 pic16c6x example 10-2: pwm period and duty cycle calculation desired pwm frequency is 78.125 khz, fosc = 20 mhz tmr2 prescale = 1 1/78.125 khz = [(pr2) + 1] ?4 ?1/20 mhz ?1 12.8 m s = [(pr2) + 1] ?4 ?50 ns ?1 pr2 = 63 find the maximum resolution of the duty cycle that can be used with a 78.125 khz frequency and 20 mhz oscillator: 1/78.125 khz = 2 pwm resolution ?1/20 mhz ?1 12.8 m s= 2 pwm resolution ?50 ns ?1 256 = 2 pwm resolution log(256) = (pwm resolution) ?log(2) 8.0 = pwm resolution at most, an 8-bit resolution duty cycle can be obtained from a 78.125 khz frequency and a 20 mhz oscillator, i.e., 0 ccpr1l:ccp1con<5:4> 255. any value greater than 255 will result in a 100% duty cycle. in order to achieve higher resolution, the pwm fre- quency must be decreased. in order to achieve higher pwm frequency, the resolution must be decreased. table 10-3 lists example pwm frequencies and resolu- tions for fosc = 20 mhz. the tmr2 prescaler and pr2 values are also shown. 10.3.3 set-up for pwm operation the following steps should be taken when con?uring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 regis- ter. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. con?ure the ccp1 module for pwm operation. table 10-3: example pwm frequencies and resolutions at 20 mhz table 10-4: registers associated with timer1, capture and compare pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1111 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 add name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (2) (3) rcif (1) txif (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh (4) pir2 ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (2) (3) rcie (1) txie (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh (4) pie2 ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh (4) ccpr2l capture/compare/pwm2 (lsb) xxxx xxxx uuuu uuuu 1ch (4) ccpr2h capture/compare/pwm2 (msb) xxxx xxxx uuuu uuuu 1dh (4) ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0? shaded cells are not used in these modes. note 1: these bits are associated with the usart module, which is implemented on the pic16c63/r63/65/65a/r65/66/67 only. 2: bits pspie and pspif are reserved on the pic16c62/62a/r62/63/r63/66, always maintain these bits clear. 3: the pir1<6> and pie1<6> bits are reserved, always maintain these bits clear. 4: these registers are associated with the ccp2 module, which is only implemented on the pic16c63/r63/65/65a/r65/66/67.
pic16c6x ds30234d-page 82 1997 microchip technology inc. table 10-5: registers associated with pwm and timer2 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (2) (3) rcif (1) txif (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh (4) pir2 ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (2) (3) rcie (1) txie (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh (4) pie2 ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 modules register 0000 0000 0000 0000 92h pr2 timer2 modules period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh (4) ccpr2l capture/compare/pwm2 (lsb) xxxx xxxx uuuu uuuu 1ch (4) ccpr2h capture/compare/pwm2 (msb) xxxx xxxx uuuu uuuu 1dh (4) ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0? shaded cells are not used in this mode. note 1: these bits are associated with the usart module, which is implemented on the pic16c63/r63/65/65a/r65/66/67 only. 2: bits pspie and pspif are reserved on the pic16c62/62a/r62/63/r63/66, always maintain these bits clear. 3: the pir1<6> and pie1<6> bits are reserved, always maintain these bits clear. 4: these registers are associated with the ccp2 module, which is only implemented on the pic16c63/r63/65/65a/r65/66/67.
1997 microchip technology inc. ds30234d-page 83 pic16c6x 11.0 synchronous serial port (ssp) module 11.1 ssp mod ule over vie w the synchronous serial port (ssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display driv- ers, a/d converters, etc. the ssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) the ssp module in i 2 c mode works the same in all pic16c6x devices that have an ssp module. however the ssp module in spi mode has differences between the pic16c66/67 and the other pic16c6x devices. the register de?itions and operational description of spi mode has been split into two sections because of the differences between the pic16c66/67 and the other pic16c6x devices. the default reset values of both the spi modules is the same regardless of the device: 11.2 spi mode for pic16c62/62a/r62/63/r63/64/ 64a/r64/65/65a/r65 .......................................84 11.3 spi mode for pic16c66/67..............................89 11.4 i2c overview ................................................95 11.5 ssp i2c operation...........................................99 refer to application note an578, ?se of the ssp mod- ule in the i 2 c multi-master environment. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 84 1997 microchip technology inc. 11.2 spi mode f or pic16c62/62a/r62/63/ r63/64/64a/r64/65/65a/r65 this section contains register de?itions and opera- tional characteristics of the spi module for the pic16c62, pic16c62a, pic16cr62, pic16c63, pic16cr63, pic16c64, pic16c64a, pic16cr64, pic16c65, pic16c65a, pic16cr65. figure 11-1: sspstat: sync serial port status register (address 94h) u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 d/a p s r/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5: d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is valid from the address match to the next start bit, stop bit, or a ck bit. 1 = read 0 = write bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 85 pic16c6x figure 11-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive over?w detect bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over?w, the data in sspsr register is lost. over?w can only occur in slave mode. the user must read the ssp- buf, even if only transmitting data, to avoid setting over?w. in master mode the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don? care" in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5: sspen : synchronous serial port enable bit in spi mode 1 = enables serial port and con?ures sck, sdo, and sdi as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and con?ures the sda and scl pins as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in both modes, when enabled, these pins must be properly con?ured as input or output. bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level. transmit happens on falling edge, receive on rising edge. 0 = idle state for clock is a low level. transmit happens on rising edge, receive on falling edge. in i 2 c mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = fosc/4 0001 = spi master mode, clock = fosc/16 0010 = spi master mode, clock = fosc/64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. s s pin control enabled. 0101 = spi slave mode, clock = sck pin. s s pin control disabled. s s can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c firmware controlled master mode (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 86 1997 microchip technology inc. 11.2.1 operation of ssp module in spi mode the spi mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. to accomplish communication, typically three pins are used: serial data out (sdo) serial data in (sdi) serial clock (sck) additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>). these control bits allow the following to be speci?d: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (output/input data on the rising/ falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that byte is moved to the sspbuf register. then the buffer full bit, bf (sspstat<0>) and ?g bit sspif are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit, wcol (sspcon<7>) will be set. user software must clear bit wcol so that it can be determined if the following write(s) to the sspbuf completed successfully. when the application software is expecting to receive valid data, the sspbuf register should be read before the next byte of data to transfer is written to the sspbuf register. the buffer full bit bf (sspstat<0>) indicates when the sspbuf register has been loaded with the received data (transmission is complete). when the sspbuf is read, bit bf is cleared. this data may be irrelevant if the spi is only a transmitter. generally the ssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf register must be read and/or writ- ten. if the interrupt method is not going to be used, then software polling can be done to ensure that a write col- lision does not occur. example 11-1 shows the loading of the sspbuf (sspsr) register for data transmis- sion. the shaded instruction is only required if the received data is meaningful. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 example 11-1: loading the sspbuf (sspsr) register the block diagram of the ssp module, when in spi mode (figure 11-3), shows that the sspsr register is not directly readable or writable, and can only be accessed from addressing the sspbuf register. addi- tionally, the ssp status register (sspstat) indicates the various status conditions. figure 11-3: ssp block diagram (spi mode) bsf status, rp0 ;specify bank 1 loop btfss sspstat, bf ;has data been ;received ;(transmit ;complete)? goto loop ;no bcf status, rp0 ;specify bank 0 movf sspbuf, w ;w reg = contents ;of sspbuf movwf rxdata ;save in user ram movf txdata, w ;w reg = contents ; of txdata movwf sspbuf ;new data to xmit read write internal data bus rc4/sdi/sda rc5/sdo ra5/ss rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 87 pic16c6x to enable the serial port, ssp enable bit sspen (sspcon<5>) must be set. to reset or recon?ure spi mode, clear enable bit sspen, re-initialize sspcon register, and then set enable bit sspen. this con?- ures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the tris reg- ister) appropriately programmed. that is: sdi must have trisc<4> set sdo must have trisc<5> cleared sck (master mode) must have trisc<3> cleared sck (slave mode) must have trisc<3> set ?s must have trisa<5> set (if implemented) any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. an example would be in master mode where you are only sending data (to a display driver), then both sdi and ss could be used as general purpose outputs by clearing their corresponding tris register bits. figure 11-4 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data slave sends dummy data master sends data slave sends data master sends dummy data slave sends data the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2) is to broadcast data by the software protocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sck output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?ine activity monitor mode. in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched interrupt ?g bit sspif (pir1<3>) is set. the clock polarity is selected by appropriately program- ming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 11-5 and figure 11-6 where the msb is trans- mitted ?st. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: fosc/4 (or t cy ) fosc/16 (or 4 t cy ) fosc/64 (or 16 t cy ) timer2 output/2 this allows a maximum bit clock frequency (at 20 mhz) of 5 mhz. when in slave mode the external clock must meet the minimum high and low times. in sleep mode, the slave can transmit and receive data and wake the device from sleep. figure 11-4: spi master/slave connection serial input buffer (sspbuf register) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xx b serial input buffer (sspbuf register) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010x b serial clock applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 88 1997 microchip technology inc. the s s pin allows a synchronous slave mode. the spi must be in slave mode (sspcon<3:0> = 04h) and the trisa<5> bit must be set the for synchro- nous slave mode to be enabled. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the mid- dle of a transmitted byte, and becomes a ?ating output. if the ss pin is taken low without resetting spi mode, the transmission will continue from the point at which it was taken high. external pull-up/ pull-down resistors may be desirable, depending on the application. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be con?ured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus con?ct. figure 11-5: spi mode timing, master mode or slave mode w/o ss control figure 11-6: spi mode timing, slave mode with ss control table 11-1: registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (2) (3) rcif (1) txif (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (2) (3) rcie (1) txie (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa porta data direction register --11 1111 --11 1111 87h trisc portc data direction register 1111 1111 1111 1111 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by ssp module in spi mode. note 1: these bits are associated with the usart which is implemented on the pic16c63/r63/65/65a/r65 only. 2: pspif and pspie are reserved on the pic16c62/62a/r62/63/r63, always maintain these bits clear. 3: pir1<6> and pie1<6> are reserved, always maintain these bits clear. sck (ckp = 0) sck (ckp = 1) sdo sdi sspif bit7 bit7 bit0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 0) sck (ckp = 1) sdo sdi sspif bit7 bit7 bit0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ss applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 89 pic16c6x 11.3 spi mode f or pic16c66/67 this section contains register de?itions and opera- tional characterisitics of the spi module on the pic16c66 and pic16c67 only. figure 11-7: sspstat: sync serial port status register (address 94h)(pic16c66/67) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p s r/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: smp: spi data input sample phase spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi sla v e mode smp must be cleared when spi is used in slave mode bit 6: cke : spi clock edge select (figure 11-11, figure 11-12, and figure 11-13) ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5: d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, or when the start bit is detected last, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, or when the stop bit is detected last, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or a ck bit. 1 = read 0 = write bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 90 1997 microchip technology inc. figure 11-8: sspcon: sync serial port control register (address 14h)(pic16c66/67) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive over?w indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over- ?w, the data in sspsr is lost. over?w can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting over?w. in master mode the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don? care" in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5: sspen : synchronous serial port enable bit in spi mode 1 = enables serial port and con?ures sck, sdo, and sdi as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and con?ures the sda and scl pins as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in both modes, when enabled, these pins must be properly con?ured as input or output. bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c firmware controlled master mode (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 91 pic16c6x 11.3.1 ssp module in spi mode for pic16c66/67 the spi mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. to accomplish communication, typically three pins are used: serial data out (sdo) rc5/sdo serial data in (sdi) rc4/sdi/sda serial clock (sck) rc3/sck/scl additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) ra5/ss when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the fol- lowing to be speci?d: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb ?st. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8-bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit bf (sspstat<0>) and interrupt ?g bit sspif (pir1<3>) are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit wcol (sspcon<7>) will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed success- fully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit bf (sspstat<0>) indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, bit bf is cleared. this data may be irrelevant if the spi is only a transmitter. generally the ssp interrupt is used to determine when the transmission/reception has completed. the sspbuf must be read and/or writ- ten. if the interrupt method is not going to be used, then software polling can be done to ensure that a write col- lision does not occur. example 11-2 shows the loading of the sspbuf (sspsr) for data transmission. the shaded instruction is only required if the received data is meaningful. example 11-2: loading the sspbuf (sspsr) register (pic16c66/67) bcf status, rp1 ;specify bank 1 bsf status, rp0 ; loop btfss sspstat, bf ;has data been ;received ;(transmit ;complete)? goto loop ;no bcf status, rp0 ;specify bank 0 movf sspbuf, w ;w reg = contents ; of sspbuf movf txdata, w ;w reg = contents ; of txdata movwf sspbuf ;new data to xmit the block diagram of the ssp module, when in spi mode (figure 11-9), shows that the sspsr is not directly readable or writable, and can only be accessed from addressing the sspbuf register. additionally, the ssp status register (sspstat) indicates the various status conditions. figure 11-9: ssp block diagram (spi mode)(pic16c66/67) movwf rxdata ;save in user ram read write internal data bus rc4/sdi/sda rc5/sdo ra5/s s rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 92 1997 microchip technology inc. to enable the serial port, ssp enable bit, sspen (sspcon<5>) must be set. to reset or recon?ure spi mode, clear bit sspen, re-initialize the sspcon reg- ister, and then set bit sspen. this con?ures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appro- priately programmed. that is: sdi must have trisc<4> set sdo must have trisc<5> cleared sck (master mode) must have trisc<3> cleared sck (slave mode) must have trisc<3> set ?s must have trisa<5> set any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. an example would be in master mode where you are only sending data (to a display driver), then both sdi and ss could be used as general purpose outputs by clearing their corresponding tris register bits. figure 11-10 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock. both processors should be programmed to same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application ?mware. this leads to three scenarios for data transmission: master sends data slave sends dummy data master sends data slave sends data master sends dummy data slave sends data the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2) is to broadcast data by the ?mware protocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sck output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?ine activity monitor mode. in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched the interrupt ?g bit sspif (pir1<3>) is set. the clock polarity is selected by appropriately program- ming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 11-11, figure 11-12, and figure 11-13 where the msb is transmitted ?st. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ? osc /4 (or t cy ) ? osc /16 (or 4 ?t cy ) ? osc /64 (or 16 ?t cy ) timer2 output/2 this allows a maximum bit clock frequency (at 20 mhz) of 5 mhz. when in slave mode the external clock must meet the minimum high and low times. in sleep mode, the slave can transmit and receive data and wake the device from sleep. figure 11-10: spi master/slave connection (pic16c66/67) serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xx b serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010x b serial clock applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 93 pic16c6x the ss pin allows a synchronous slave mode. the spi must be in slave mode (sspcon<3:0> = 04h) and the trisa<5> bit must be set for the synchro- nous slave mode to be enabled. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ?ating output. if the s s pin is taken low without resetting spi mode, the transmission will continue from the point at which it was taken high. external pull-up/ pull-down resistors may be desirable, depending on the applica- tion. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be con?ured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus con?ct. note: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note: if the spi is used in slave mode with cke = '1', then the ss pin control must be enabled. figure 11-11: spi mode timing, master mode (pic16c66/67) figure 11-12: spi mode timing (slave mode with cke = 0) (pic16c66/67) sck (ckp = 0, sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sdi (smp = 1) sck (ckp = 0, sck (ckp = 1, sck (ckp = 1, sdo bit7 bit7 bit0 bit0 cke = 0) cke = 1) cke = 0) cke = 1) sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss (optional) applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 94 1997 microchip technology inc. figure 11-13: spi mode timing (slave mode with cke = 1) (pic16c66/67) table 11-2: registers associated with spi operation (pic16c66/67) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa porta data direction register --11 1111 --11 1111 87h trisc portc data direction register 1111 1111 1111 1111 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by ssp module in spi mode. note 1: pspif and pspie are reserved on the pic16c66, always maintain these bits clear. 2: pir1<6> and pie1<6> are reserved, always maintain these bits clear. sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss (not optional) applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 95 pic16c6x 11.4 i 2 c over vie w this section provides an overview of the inter-inte- grated circuit (i 2 c) bus, with section 11.5 discussing the operation of the ssp module in i 2 c mode. the i 2 c bus is a two-wire serial interface developed by the philips corporation. the original speci?ation, or standard mode, was for data transfers of up to 100 kbps. the enhanced speci?ation (fast mode) is also supported. this device will communicate with both standard and fast mode devices if attached to the same bus. the clock will determine the data rate. the i 2 c interface employs a comprehensive protocol to ensure reliable transmission and reception of data. when transmitting data, one device is the ?aster which initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the ?lave. all portions of the slave protocol are implemented in the ssp modules hard- ware, except general call support, while portions of the master protocol need to be addressed in the pic16cxx software. table 11-3 de?es some of the i 2 c bus terminology. for additional information on the i 2 c interface speci?ation, refer to the philips docu- ment the i 2 c bus and how to use it. #939839340011, which can be obtained from the philips corporation. in the i 2 c interface protocol each device has an address. when a master wishes to initiate a data trans- fer, it ?st transmits the address of the device that it wishes to ?alk to. all devices ?isten to see if this is their address. within this address, a bit speci?s if the master wishes to read-from/write-to the slave device. the master and slave are always in opposite modes (transmitter/receiver) of operation during a data trans- fer. that is they can be thought of as operating in either of these two relations: master-transmitter and slave-receiver slave-transmitter and master-receiver in both cases the master generates the clock signal. the output stages of the clock (scl) and data (sda) lines must have an open-drain or open-collector in order to perform the wired-and function of the bus. external pull-up resistors are used to ensure a high level when no device is pulling the line down. the num- ber of devices that may be attached to the i 2 c bus is limited only by the maximum bus loading speci?ation of 400 pf. 11.4.1 initiating and terminating data transfer during times of no data transfer (idle time), both the clock line (scl) and the data line (sda) are pulled high through the external pull-up resistors. the start and stop conditions determine the start and stop of data transmission. the start condition is de?ed as a high to low transition of the sda when the scl is high. the stop condition is de?ed as a low to high transition of the sda when the scl is high. figure 11-14 shows the start and stop conditions. the master generates these conditions for starting and terminating data trans- fer. due to the de?ition of the start and stop con- ditions, when data is being transmitted, the sda line can only change state when the scl line is low. figure 11-14: start and stop conditions sda scl s p start condition change of data allowed change of data allowed stop condition table 11-3: i 2 c bus terminology term description transmitter the device that sends the data to the bus. receiver the device that receives the data from the bus. master the device which initiates the transfer, generates the clock and terminates the transfer. slave the device addressed by a master. multi-master more than one master device in a system. these masters can attempt to control the bus at the same time without corrupting the message. arbitration procedure that ensures that only one of the master devices will control the bus. this ensure that the transfer data does not get corrupted. synchronization procedure where the clock signals of two or more devices are synchronized. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 96 1997 microchip technology inc. 11.4.2 addressing i 2 c devices there are two address formats. the simplest is the 7-bit address format with a r/w bit (figure 11-15). the more complex is the 10-bit address with a r/w bit (figure 11-16). for 10-bit address format, two bytes must be transmitted with the ?st ?e bits specifying this to be a 10-bit address. figure 11-15: 7-bit address format figure 11-16: i 2 c 10-bit address format 11.4.3 transfer acknowledge all data must be transmitted per byte, with no limit to the number of bytes transmitted per data transfer. after each byte, the slave-receiver generates an acknowl- edge bit (a ck ) (figure 11-17). when a slave-receiver doesn? acknowledge the slave address or received data, the master must abort the transfer. the slave must leave sda high so that the master can generate the stop condition (figure 11-14). s r/w ack sent by slave slave address s r/w read/write pulse msb lsb start condition ack acknowledge s 1 1 1 1 0 a9 a8 r/w a ck a7 a6 a5 a4 a3 a2 a1 a0 a ck sent by slave = 0 for write s r/w a ck - start condition - read/write pulse - acknowledge figure 11-17: slave-receiver acknowledge if the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. to signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). the slave then releases the sda line so the master can generate the stop condition. the master can also generate the stop condition during the acknowledge pulse for valid termination of data transfer. if the slave needs to delay the transmission of the next byte, holding the scl line low will force the master into a wait state. data transfer continues when the slave releases the scl line. this allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. this wait state tech- nique can also be implemented at the bit level, figure 11-18. the slave will inherently stretch the clock, when it is a transmitter, but will not when it is a receiver. the slave will have to clear the sspcon<4> bit to enable clock stretching when it is a receiver. s data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment not acknowledge acknowledge 1 2 8 9 figure 11-18: data transfer wait state 12 78 9 123 89 p sda scl s start condition address r/w ack wait state data ack msb acknowledgment signal from receiver acknowledgment signal from receiver byte complete interrupt with receiver clock line held low while interrupts are serviced stop condition applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 97 pic16c6x figure 11-19 and figure 11-20 show master-transmit- ter and master-receiver data transfer sequences. when a master does not wish to relinquish the bus (by generating a stop condition), a repeated start con- dition (sr) must be generated. this condition is identi- cal to the start condition (sda goes high-to-low while scl is high), but occurs after a data transfer acknowl- edge pulse (not the bus-free state). this allows a mas- ter to send ?ommands to the slave and then receive the requested information or to address a different slave device. this sequence is shown in figure 11-21. figure 11-19: master-transmitter sequence figure 11-20: master-receiver sequence figure 11-21: combined format for 7-bit address: s slave address first 7 bits s r/w a1 slave address second byte a2 data a data p a master transmitter addresses a slave receiver with a 10-bit address. a/a slave address r/w a data a data a/a p '0' (write) data transferred (n bytes - acknowledge) a master transmitter addresses a slave receiver with a 7-bit address. the transfer direction is not changed. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: for 7-bit address: s slave address first 7 bits s r/w a1 slave address second byte a2 a master transmitter addresses a slave receiver with a 10-bit address. slave address r/w a data a data a p '1' (read) data transferred (n bytes - acknowledge) a master reads a slave immediately after the ?st byte. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: slave address first 7 bits sr r/w a3 a data a p data (read) combined format: s combined format - a master addresses a slave with a 10-bit address, then transmits slave address r/w a data a/a sr p (read) sr = repeated transfer direction of data and acknowledgment bits depends on r/w bits. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition slave address first 7 bits sr r/w a (write) data to this slave and reads data from this slave. slave address second byte data sr slave address first 7 bits r/w a data a a p a a data a/a data (read) slave address r/w a data a/a start condition (write) direction of transfer may change at this point (read or write) (n bytes + acknowledge) applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 98 1997 microchip technology inc. 11.4.4 multi-master the i 2 c protocol allows a system to have more than one master. this is called multi-master. when two or more masters try to transfer data at the same time, arbi- tration and synchronization occur. 11.4.4.1 arbitration arbitration takes place on the sda line, while the scl line is high. the master which transmits a high when the other master transmits a low loses arbitration (figure 11-22), and turns off its data output stage. a master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. when the master devices are addressing the same device, arbitration continues into the data. figure 11-22: multi-master arbitration (two masters) masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. this is because the winning mas- ter-transmitter may be addressing it. arbitration is not allowed between: a repeated start condition a stop condition and a data bit a repeated start condition and a stop condi- tion care needs to be taken to ensure that these conditions do not occur. transmitter 1 loses arbitration data 1 sda data 1 data 2 sda scl 11.2.4.2 clock synchronization clock synchronization occurs after the devices have started arbitration. this is performed using a wired- and connection to the scl line. a high to low transition on the scl line causes the concerned devices to start counting off their low period. once a device clock has gone low, it will hold the scl line low until its scl high state is reached. the low to high transition of this clock may not change the state of the scl line, if another device clock is still within its low period. the scl line is held low by the device with the longest low period. devices with shorter low periods enter a high wait- state, until the scl line comes high. when the scl line comes high, all devices start counting off their high periods. the ?st device to complete its high period will pull the scl line low. the scl line high time is deter- mined by the device with the shortest high period, figure 11-23. figure 11-23: clock synchronization clk 1 clk 2 scl wait state start counting high period counter reset applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 99 pic16c6x 11.5 ssp i 2 c operation the ssp module in i 2 c mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate ?mware implementations of the master functions. the ssp module implements the standard mode speci?a- tions as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/sck/ scl pin, which is the clock (scl), and the rc4/sdi/ sda pin, which is the data (sda). the user must con- ?ure these pins as inputs or outputs through the trisc<4:3> bits. the ssp module functions are enabled by setting ssp enable bit sspen (ssp- con<5>). figure 11-24: ssp block diagram (i 2 c mode) the ssp module has ?e registers for i 2 c operation. these are the: ssp control register (sspcon) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly acces- sible ssp address register (sspadd) read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ? 2 c slave mode (7-bit address) ? 2 c slave mode (10-bit address) ? 2 c slave mode (7-bit address), with start and stop bit interrupts enabled ? 2 c slave mode (10-bit address), with start and stop bit interrupts enabled ? 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. the sspstat register gives the status of the data transfer. this information includes detection of a start or stop bit, speci?s if the received byte was data or address if the next byte is the completion of 10- bit address, and if this will be a read or write data trans- fer. the sspstat register is read only. the sspbuf is the register to which transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf register and ?g bit sspif is set. if another complete byte is received before the sspbuf register is read, a receiver over?w has occurred and bit sspov (sspcon<6>) is set and the byte in the sspsr is lost. the sspadd register holds the slave address. in 10-bit mode, the user first needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 100 1997 microchip technology inc. 11.5.1 slave mode in slave mode, the scl and sda pins must be con?- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (a ck ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this a ck pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the over?w bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 11-4 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user soft- ware did not properly clear the over?w condition. flag bit bf is cleared by reading the sspbuf register while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c speci?ation as well as the requirement of the ssp module is shown in timing parameter #100 and param- eter #101. 11.5.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an a ck pulse is generated. d) ssp interrupt ?g bit, sspif (pir1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave (figure 11-16). the ?e most sig- ni?ant bits (msbs) of the ?st address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the sec- ond address byte. for a 10-bit address the ?st byte would equal 1111 0 a9 a8 0 ? where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7- 9 for slave- transmitter: 1. receive ?st (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the ?st (high) byte of address, if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 7. receive repeated start condition. 8. receive ?st (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear ?g bit sspif. table 11-4: data transfer received byte actions status bits as data transfer is received sspsr ? sspbuf generate a ck pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 no no ye s applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 101 pic16c6x 11.5.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat reg- ister is cleared. the received address is loaded into the sspbuf register. when the address byte over?w condition exists, then no acknowledge (a ck ) pulse is given. an over?w con- dition is de?ed as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. figure 11-25: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read a ck receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w =0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) a ck a ck is not sent. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 102 1997 microchip technology inc. 11.5.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the a ck pulse will be sent on the ninth bit, and pin rc3/sck/scl is held low. the transmit data must be loaded into the ssp- buf register, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretch- ing the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 11-26). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software, and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the a ck pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not a ck ), then the data transfer is complete. when the a ck is latched by the slave, the slave logic is reset (resets sspstat reg- ister) and the slave then monitors for another occur- rence of the start bit. if the sda line was low (a ck ), the transmit data must be loaded into the sspbuf reg- ister, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp. figure 11-26: i 2 c waveforms for transmission (7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 a ck d7 d6 d5 d4 d3 d2 d1 d0 a ck transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set) applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 103 pic16c6x 11.5.2 master mode master mode of operation is supported in firmware using interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop condi- tions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master mode the scl and sda lines are manipu- lated by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irrespective of the value(s) in portc<4:3>. so when transmitting data, a '1' data bit must have the trisc<4> bit set (input) and a '0' data bit must have the trisc<4> bit cleared (out- put). the same scenario is true for the scl line with the trisc<3> bit. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received master mode of operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ) or with the slave active. when both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. 11.5.3 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost, these are: address transfer data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address trans- fer stage, communication to the device may be in progress. if addressed an a ck pulse will be generated. if arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. table 11-5: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp (3) cke (3) d/a p s r/w ua bf 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by ssp module in spi mode. note 1: pspif and pspie are reserved on the pic16c66, always maintain these bits clear. 2: pir1<6> and pie1<6> are reserved, always maintain these bits clear. 3: the smp and cke bits are implemented on the pic16c66/67 only. all other pic16c6x devices have these two bits unim- plemented, read as '0'. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
pic16c6x ds30234d-page 104 1997 microchip technology inc. figure 11-27: operation of the i 2 c module in idle_mode, rcv_mode or xmit_mode i dle_mode (7-bit): if (addr_match) { set interrupt; if (r/w = 1) { send a ck = 0; set xmit_mode; } else if (r/w = 0) set rcv_mode; } rcv_mode: if ((sspbuf=full) or (sspov = 1)) { set sspov; do not acknowledge; } else { transfer sspsr ? sspbuf; send a ck = 0; } receive 8-bits in sspsr; set interrupt; xmit_mode: while ((sspbuf = empty) and (ckp=0)) hold scl low; send byte; set interrupt; if ( a ck received = 1) { end of transmission; go back to idle_mode; } else if ( a ck received = 0) go back to xmit_mode; idle_mode (10-bit): if (high_byte_addr_match and (r/w = 0)) { prior_addr_match = false; set interrupt; if ((sspbuf = full) or ((sspov = 1)) { set sspov; do not acknowledge; } else { set ua = 1; send a ck = 0; while (sspadd not updated) hold scl low; clear ua = 0; receive low_addr_byte; set interrupt; set ua = 1; if (low_byte_addr_match) { prior_addr_match = true; send a ck = 0; while (sspadd not updated) hold scl low; clear ua = 0; set rcv_mode; } } } else if (high_byte_addr_match and (r/w = 1) { if (prior_addr_match) { send a ck = 0; set xmit_mode; } else prior_addr_match = false; } applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67
1997 microchip technology inc. ds30234d-page 105 pic16c6x 12.0 universal synchronous asynchronous receiver transmitter (usart) module the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci) the usart can be con- ?ured as a full duplex asynchronous system that can communicate with peripheral devices such as crt ter- applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 minals and personal computers, or it can be con?ured as a half duplex synchronous system that can commu- nicate with peripheral devices such as a/d or d/a inte- grated circuits, serial eeproms etc. the usart can be con?ured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) bit spen (rcsta<7>) and bits trisc<7:6> have to be set in order to con?ure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchro- nous receiver transmitter. figure 12-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync brgh trmt tx9d r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: csrc : clock source select bit asynchronous mode don? care synchronous mode 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6: tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4: sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3: unimplemented: read as '0' bit 2: brgh : high baud rate select bit asynchronous mode 1 = high speed note: for the pic16c63/r63/65/65a/r65 the asynchronous high speed mode (brgh = 1) may experience a high rate of receive errors. it is recommended that brgh = 0. if you desire a higher baud rate than brgh = 0 can support, refer to the device errata for additional infor- mation or use the pic16c66/67. 0 = low speed synchronous mode unused in this mode bit 1: trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data. can be parity bit.
pic16c6x ds30234d-page 106 1997 microchip technology inc. figure 12-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-x spen rx9 sren cren ferr oerr rx9d r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset x = unknown bit7 bit0 bit 7: spen : serial port enable bit (con?ures rc7/rx/dt and rc6/tx/ck pins as serial port pins when bits trisc<7:6> are set) 1 = serial port enabled 0 = serial port disabled bit 6: rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit asynchronous mode don? care synchronous mode - master 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - sla v e unused in this mode bit 4: cren : continuous receive enable bit asynchronous mode 1 = enables continuous receive 0 = disables continuous receive synchronous mode 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3: unimplemented: read as '0' bit 2: ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0: rx9d : 9th bit of received data (can be parity bit)
1997 microchip technology inc. ds30234d-page 107 pic16c6x 12.1 usar t b aud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode bit brgh (txsta<2>) also controls the baud rate. in synchronous mode bit brgh is ignored. table 12-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and fosc, the nearest inte- ger value for the spbrg register can be calculated using the formula in table 12-1. from this, the error in baud rate can be determined. example 12-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 example 12-1: calculating baud rate error it may be advantageous to use the high baud rate (brgh = 1) even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register, causes the brg timer to be reset (or cleared), this ensures that the brg does not wait for a timer over?w before output- ting the new baud rate. note: for the pic16c63/r63/65/65a/r65 the asynchronous high speed mode (brgh = 1) may experience a high rate of receive errors. it is recommended that brgh = 0. if you desire a higher baud rate than brgh = 0 can support, refer to the device errata for additional information or use the pic16c66/67. desired baud rate = fosc / (64 (x + 1)) 9600 = 16000000 /(64 (x + 1)) x= ? 25.042 ? = 25 calculated baud rate=16000000 / (64 (25 + 1)) = 9615 error = (calculated baud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 = 0.16% table 12-1: baud rate formula table 12-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate = f osc /(16(x+1)) n/a x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used by the brg.
pic16c6x ds30234d-page 108 1997 microchip technology inc. table 12-3: baud rates for synchronous mode table 12-4: baud rates for asynchronous mode (brgh = 0) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 na - - na - - na - - na - - 2.4 na - - na - - na - - na - - 9.6 na - - na - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500 0 9 500 0 7 500 0 4 na - - high 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 low 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 baud rate (k) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 0.303 +1.14 26 1.2 na - - na - - na - - 1.202 +0.16 207 1.170 -2.48 6 2.4 na - - na - - na - - 2.404 +0.16 103 na - - 9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 na - - 19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 na - - 76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 na - - 96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 na - - na - - 300 316.8 +5.60 3 na - - 298.3 -0.57 2 na - - na - - 500 na - - na - - na - - na - - na - - high 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0 low 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255 baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 na - - 96 104.2 +8.51 2 na - - na - - na - - 300 312.5 +4.17 0 na - - na - - na - - 500 na - - na - - na - - na - - high 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 low 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 baud rate (k) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 na - - 2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 na - - 9.6 9.9 +3.13 7 na - - 9.322 -2.90 5 na - - na - - 19.2 19.8 +3.13 3 na - - 18.64 -2.90 2 na - - na - - 76.8 79.2 +3.13 0 na - - na - - na - - na - - 96 na - - na - - na - - na - - na - - 300 na - - na - - na - - na - - na - - 500 na - - na - - na - - na - - na - - high 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0 low 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255
1997 microchip technology inc. ds30234d-page 109 pic16c6x table 12-5: baud rates for asynchronous mode (brgh = 1) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.16 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 250 0 4 250 0 3 na - - na - - 625 625 0 1 na - - 625 0 0 na - - 1250 1250 0 0 na - - na - - na - - baud rate (k) f osc = 5.068 mhz spbrg value (decimal) 4 mhz spbrg value (decimal) 3.579 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error kbaud % error 9.6 9.6 0 32 na - - 9.727 +1.32 22 8.928 -6.99 6 na - - 19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 na - - 38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 na - - 57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 na - - 115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 na - - na - - 250 na - - na - - 223.721 -10.51 0 na - - na - - 625 na - - na - - na - - na - - na - - 1250 na - - na - - na - - na - - na - - note: for the pic16c63/r63/65/65a/r65 the asynchronous high speed mode (brgh = 1) may experience a high rate of receive errors. it is recommended that brgh = 0. if you desire a higher baud rate than brgh = 0 can support, refer to the device errata for additional information or use the pic16c66/67.
pic16c6x ds30234d-page 110 1997 microchip technology inc. 12.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. if bit brgh (txsta<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth fall- ing edges of a x16 clock (figure 12-3). if bit brgh is set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge after the ?st falling edge of a x4 clock (figure 12-4 and figure 12-5). figure 12-3: rx pin sampling scheme (brgh = 0) pic16c63/r63/65/65a/r65) figure 12-4: rx pin sampling scheme (brgh = 1) (pic16c63/r63/65/65a/r65) figure 12-5: rx pin sampling scheme (brgh = 1) (pic16c63/r63/65/65a/r65) rx baud clk x16 clk start bit bit0 samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 baud clk for all but start bit (rc7/rx/dt pin) rc7/rx/dt pin baud clk x4 clk q2, q4 clk start bit bit0 bit1 first falling edge after rx pin goes low second rising edge samples samples samples 1234123412 rc7/rx/dt pin baud clk x4 clk q2, q4 clk start bit bit0 first falling edge after rx pin goes low second rising edge samples 12 3 4 baud clk for all but start bit
1997 microchip technology inc. ds30234d-page 111 pic16c6x figure 12-6: rx pin sampling scheme (brgh = 0 or = 1) (pic16c66/67) rx baud clk x16 clk start bit bit0 samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 baud clk for all but start bit (rc7/rx/dt pin)
pic16c6x ds30234d-page 112 1997 microchip technology inc. 12.2 usar t a sync hr onous mode in this mode, the usart uses standard nonreturn-to- zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb first. the usarts transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 12.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 12-7. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ) the txreg register is empty and ?g bit txif (pir1<4>) is set. this interrupt is enabled/dis- applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 abled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while ?g bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>) shows the status of the tsr register. status bit trmt is a read only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr reg- ister is empty. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 12-7). the transmission can also be started by ?st loading the txreg register and then setting enable bit txen. normally when transmission is ?st started, the tsr register is empty, so a transfer to the txreg register will result in an immediate trans- fer to tsr register resulting in an empty txreg regis- ter. a back-to-back transfer is thus possible (figure 12- 9). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result the rc6/tx/ck pin will revert to hi-impedance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit maybe loaded in the tsr regis- ter. note 1: the tsr register is not mapped in data memory so it is not available to the user. note 2: flag bit txif is set when enable bit txen is set. figure 12-7: usart transmit block diagram txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8
1997 microchip technology inc. ds30234d-page 113 pic16c6x steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, then set bit brgh. (section 12.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 12-8: asynchronous master transmission figure 12-9: asynchronous master transmission (back to back) table 12-6: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: pspif and pspie are reserved on the pic16c63/r63/66, always maintain these bits clear. 2: pir1<6> and pie1<6> are reserved, always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg reg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty ?g) trmt bit (transmit shift reg. empty ?g) transmit shift reg. write to txreg reg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. ?g) trmt bit (transmit shift reg. empty ?g) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions.
pic16c6x ds30234d-page 114 1997 microchip technology inc. 12.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 12-10. the data comes in the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift reg- ister (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, ?g bit rcif (pir1<5>) is set. the actual interrupt can be enabled/disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is double buffered register, i.e., it is a two deep fifo. it is possible for two bytes of data to be received and trans- ferred to the rcreg fifo and a third byte begin shift- ing to the rsr register. on the detection of the stop bit of the third byte, if the rcreg is still full, then the overrun error bit, oerr (rcsta<1>) will be set. the word in the rsr register will be lost. the rcreg reg- ister can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in software. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhibited, so it is essential to clear overrun bit oerr if it is set. framing error bit ferr (rcsta<2>) is set if a stop bit is detected as clear. error bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg register will load bits rx9d and ferr with new values. therefore it is essential for the user to read the rcsta register bef ore reading rcreg in order not to lose the old ferr and rx9d information. figure 12-10: usart receive block diagram figure 12-11: asynchronous reception x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rc7/rx/dt (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt ?g) oerr bit cren bit word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third wor d, causing overrun error bit oerr to be set.
1997 microchip technology inc. ds30234d-page 115 pic16c6x steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 12.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting enable bit cren. 6. flag bit rcif will be set when reception is com- plete, and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. table 12-7: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: pspie and pspif are reserved on the pic16c63/r63/66, always maintain these bits clear. 2: pie1<6> and pir1<6> are reserved, always maintain these bits clear.
pic16c6x ds30234d-page 116 1997 microchip technology inc. 12.3 usar t s ync hr onous master mode in synchronous master mode the data is transmitted in a half-duplex manner i.e., transmission and reception do not occur at the same time. when transmitting data the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition enable bit spen (rcsta<7>) is set in order to con?ure the rc6 and rc7 i/o pins to ck (clock) and dt (data) lines respectively. the master mode indi- cates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 12.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 12-7. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr register is loaded with new data from the txreg register (if avail- able). once the txreg register transfers the data to the tsr register (occurs in one tcycle), the txreg register is empty and interrupt ?g bit txif (pir1<4>) is set. this interrupt can be enabled/disabled by set- ting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the status of enable bit txie and cannot be cleared in software. it will clear only when new data is loaded into the txreg register. while ?g bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. status bit trmt is a read only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr register is not mapped in data memory so it is not available to the user. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the ?st data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is sta- ble around the falling edge of the synchronous clock (figure 12-12). the transmission can also be started by ?st loading the txreg register and then setting enable bit txen (figure 12-13). this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren, and sren are clear. setting enable bit txen will start the brg, cre- ating a shift clock immediately. normally when trans- mission is ?st started, the tsr register is empty, so a transfer to the txreg register will result in an immedi- ate transfer to tsr resulting in an empty txreg reg- ister. back-to-back transfers are possible. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 clearing enable bit txen, during a transmission, will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to hi-imped- ance. if, during a transmission, either bit cren or bit sren is set the transmission is aborted and the dt pin reverts to a hi-impedance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic however, is not reset although it is disconnected from the pins. in order to reset the transmitter, the user has to clear enable bit txen. if enable bit sren is set (to interrupt an on going transmission and receive a single word), then after the single word is received, enable bit sren will be cleared, and the serial port will revert back to trans- mitting since enable bit txen is still set. the dt line will immediately switch from hi-impedance receive mode to transmit and start driving. to avoid this, enable bit txen should be cleared. in order to select 9-bit transmission, bit tx9 (txsta<6>) should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr register was empty and the txreg register was written before writing the ?ew tx9d, the ?resent value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 12.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register.
1997 microchip technology inc. ds30234d-page 117 pic16c6x table 12-8: registers associated with synchronous master transmission figure 12-12: synchronous transmission figure 12-13: synchronous transmission through txen address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for synchronous master transmission. note 1: pspie and pspif are reserved on the pic16c63/r63/66, always maintain these bits clear. 2: pie1<6> and pir1<6> are reserved, always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit (interrupt flag) trmt txen bit '1' '1' note: sync master mode; spbrg = '0'. continuous transmission of two 8-bit words word 2 trmt bit write word1 write word2 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit
pic16c6x ds30234d-page 118 1997 microchip technology inc. 12.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>) bit or enable bit cren (rcsta<4>). data is sampled on the dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the reception is continuous until bit cren is cleared. if both the bits are set then bit cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt bit rcif (pir1<5>) is set. the actual interrupt can be enabled/disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit which is reset by the hardware. in this case, it is reset when the rcreg register has been read and is empty. the rcreg is a double buffered register, i.e., it is a two deep fifo. it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit, oerr (rcsta<1>) is set. the word in the rsr register will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. overrun error bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited, so it is essential to clear bit oerr if it is set. the 9th receive bit is buffered the same way as the receive data. reading the rcreg register will load bit rx9d with a new value. therefore it is essential for the user to read the rcsta register before reading the rcreg register in order not to lose the old rx9d bit information. steps to follow when setting up synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate (section 12.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set enable bit sren. for continuous reception set enable bit cren. 7. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing enable bit cren. table 12-9: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for synchronous master reception. note 1: pspif and pspie are reserved on the pic16c63/r63/66, always maintain these bits clear. 2: pir1<6> and pie1<6> are reserved, always maintain these bits clear.
1997 microchip technology inc. ds30234d-page 119 pic16c6x figure 12-14: synchronous reception (master mode, sren) cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = '1' and bit brg = '0'. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4
pic16c6x ds30234d-page 120 1997 microchip technology inc. 12.4 usar t s ync hr onous sla ve mode synchronous slave mode differs from master mode in the fact that the shift clock is supplied externally at the ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 12.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the ?st word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the ?st word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and ?g bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the inter- rupt vector (0004h). steps to follow when setting up synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen, and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 12.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of the sleep mode. also, enable bit sren is a don't care in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen, and clearing bit csrc. 2. if interrupts are desired, then set enable bit rcie. 3. if 9-bit reception is desired, then set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete, and an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing enable bit cren.
1997 microchip technology inc. ds30234d-page 121 pic16c6x table 12-10: registers associated with synchronous slave transmission table 12-11: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for synchronous slave transmission. note 1: pspif and pspie are reserved on the pic16c63/r63/66, always maintain these bits clear. 2: pir1<6> and pie1<6> are reserved, always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for synchronous slave reception. note 1: pspif and pspie are reserved on the pic16c63/r63/66, always maintain these bits clear. 2: pir1<6> and pie1<6> are reserved, always maintain these bits clear.
pic16c6x ds30234d-page 122 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30234d-page 123 pic16c6x 13.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real- time applications. the pic16cxx family has a host of such features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving operating modes and offer code protection. these are: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep mode code protection id locations in-circuit serial programming the pic16cxx has a watchdog timer which can be shut off only through con?uration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which pro- vides a ?ed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to ? the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of con?uration bits are used to select various options. 13.1 c o n guration bits the con?uration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/con?uration memory space (2000h - 3fffh), which can be accessed only during program- ming. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 13-1: configuration word for pic16c61 cp0 pwrte wdte fosc1 fosc0 register: config address 2007h bit13 bit0 bit 13-5: unimplemented : read as '1' bit 4: cp0 : code protection bit 1 = code protection off 0 = all memory is code protected, but 00h - 3fh is writable bit 3: pwrte : power-up timer enable bit 1 = power-up timer enabled 0 = power-up timer disabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator
pic16c6x ds30234d-page 124 1997 microchip technology inc. figure 13-2: configuration word for pic16c62/64/65 figure 13-3: configuration word for pic16c62a/r62/63/r63/64a/r64/65a/r65/66/67 cp1 cp0 pwrte wdte fosc1 fosc0 register: config address 2007h bit13 bit0 bit 13-6: unimplemented : read as '1' bit 5-4: cp1:cp0 : code protection bits 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 3: pwrte : power-up timer enable bit 1 = power-up timer enabled 0 = power-up timer disabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator cp1 cp0 cp1 cp0 cp1 cp0 boden cp1 cp0 pwr te wdte fosc1 fosc0 register: config address 2007h bit13 bit0 bit 13-8: cp1:cp0 : code protection bits (2) bit 5:4 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 7: unimplemented : read as '1' bit 6: boden : brown-out reset enable bit (1) 1 = brown-out reset enabled 0 = brown-out reset disabled bit 3: pwr te : power-up timer enable bit (1) 1 = power-up timer disabled 0 = power-up timer enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt) regardless of the value of bit p wr t e . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp1:cp0 pairs have to be given the same value to implement the code protection scheme listed.
1997 microchip technology inc. ds30234d-page 125 pic16c6x 13.2 o sc illator con gurations 13.2.1 oscillator types the pic16cxx can be operated in four different oscil- lator modes. the user can program two con?uration bits (fosc1 and fosc0) to select one of these four modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc resistor/capacitor 13.2.2 crystal oscillator/ceramic resonators in lp, xt, or hs modes a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 13-4). the pic16cxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?a- tions. when in lp, xt, or hs modes, the device can have an external clock source to drive the osc1/clkin pin (figure 13-5). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 13-4: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 13-5: external clock input operation (hs, xt or lp osc configuration) c1 c2 xtal osc2 note1 osc1 r f sleep to internal logic pic16cxx rs see table 13-1, table 13-3, table 13-2 and table 13-4 for recommended values of c1 and c2. note 1: a series resistor may be required for at strip cut crystals. 2: for the pic16c61 the buffer is on the osc2 pin, all other devices have the buffer on the osc1 pin. (2) (2) to internal logic osc1 osc2 open clock from ext. system pic16cxx
pic16c6x ds30234d-page 126 1997 microchip technology inc. table 13-1: ceramic resonators pic16c61 table 13-2: ceramic resonators pic16c62/62a/r62/63/r63/64/ 64a/r64/65/65a/r65/66/67 ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 47 - 100 pf 15 - 68 pf 15 - 68 pf 47 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 15 - 68 pf 10 - 47 pf 15 - 68 pf 10 - 47 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. table 13-3: capacitor selection for crystal oscillator for pic16c61 table 13-4: capacitor selection for crystal oscillator for pic16c62/62a/r62/63/ r63/64/64a/r64/65/65a/r65/ 66/67 mode freq osc1 osc2 lp 32 khz 200 khz 33 - 68 pf 15 - 47 pf 33 - 68 pf 15 - 47 pf xt 100 khz 500 khz 1 mhz 2 mhz 4 mhz 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf hs 8 mhz 20 mhz 15 - 47 pf 15 - 47 pf 15 - 47 pf 15 - 47 pf these values are for design guidance only. see notes at bottom of page. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended values of c1 and c2 are identical to the ranges tested table 13-1 and table 13-2. 2: higher capacitance increases the stability of oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal man- ufacturer for appropriate values of external components. 4: rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci- ?ation.
1997 microchip technology inc. ds30234d-page 127 pic16c6x 13.2.3 external crystal oscillator circuit either a prepackaged oscillator can be used or a simple oscillator circuit with ttl gates can be built. prepack- aged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. figure 13-6 shows implementation of a parallel reso- nant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a par- allel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potenti- ometer biases the 74as04 in the linear region. this could be used for external oscillator designs. figure 13-6: external parallel resonant crystal oscillator circuit figure 13-7 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator cir- cuit. the 330 k w resistors provide the negative feed- back to bias the inverters in their linear region. figure 13-7: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16cxx clkin to other devices 330 k w 74as04 74as04 pic16cxx clkin to other devices xtal 330 k w 74as04 0.1 m f 13.2.4 rc oscillator for timing insensitive applications the rc device option offers additional cost savings. the rc oscillator fre- quency is a function of the supply voltage, the resistor (rext) and capacitor (cext) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process param- eter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 13-8 shows how the rc combination is con- nected to the pic16cxx. for rext values below 2.2 k w , the oscillator operation may become unstable or stop completely. for very high rext values (e.g. 1 m w ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or pack- age lead frame capacitance. see characterization data for desired device for rc fre- quency variation from part to part due to normal pro- cess variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). see characterization data for desired device for varia- tion of oscillator frequency due to v dd for given rext/ cext values as well as frequency variation due to oper- ating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic (see figure 3-5 for waveform). figure 13-8: rc oscillator mode osc2/clkout cext v dd rext v ss pic16cxx osc1 fosc/4 internal clock
pic16c6x ds30234d-page 128 1997 microchip technology inc. 13.3 r eset the pic16cxx differentiates between various kinds of reset: power-on reset (por) ? clr reset during normal operation mclr reset during sleep wdt reset (normal operation) brown-out reset (bor) - not on pic16c61/62/ 64/65 some registers are not affected in any reset condition, their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?eset state on power-on reset (por), on mclr or wdt reset, on mclr reset during sleep, and on brown- out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 the t o and p d bits are set or cleared differently in dif- ferent reset situations as indicated in table 13-7, table 13-8, and table 13-9. these bits are used in soft- ware to determine the nature of the reset. see table 13-12 for a full description of reset states of all registers. a simpli?d block diagram of the on-chip reset circuit is shown in figure 13-9. on the pic16c62a/r62/63/r63/64a/r64/65a/r65/ 66/67, the mclr reset path has a noise ?ter to detect and ignore small pulses. see parameter #34 for pulse width speci?ations. it should be noted that a wdt reset does not drive the mclr pin low. figure 13-9: simplified block diagram of on-chip reset circuit s r q external reset mclr /v pp pin v dd pin osc1/ wdt module v dd rise detect ost/pwrt on-chip rc osc wdt power-on reset ost 10-bit ripple counter pwrt chip reset 10-bit ripple counter time-out enable ost enable pwrt sleep brown-out reset boden note 1: this is a separate oscillator from the rc oscillator of the clkin pin. 2: brown-out reset is not implemented on the pic16c61/62/64/65. 3: see table 13-5 and table 13-6 for time-out situations. (2) (1) clkin pin (3)
1997 microchip technology inc. ds30234d-page 129 pic16c6x 13.4 p o wer - on reset (por), p o wer - up t imer (pwr t), o scillator star t-up timer (ost) and b r o wn-out reset ( bo r) 13.4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, just tie the mclr /v pp pin directly (or through a resistor) to v dd . this will elimi- nate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is required. see electrical speci?ations for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the startup conditions. for additional information, refer to application note an607, power-up trouble shooting . 13.4.2 power-up timer (pwrt) the power-up timer provides a ?ed 72 ms nominal time-out on power-up only, from por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as pwrt is active. the pwrts time delay allows v dd to rise to an acceptable level. a con?uration bit is provided to enable/disable the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature, and process variation. see dc parameters for details. 13.4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 13.4.4 brown-out reset (bor) a con?uration bit, boden, can disable (if clear/pro- grammed) or enable (if set) the brown-out reset cir- cuitry. if v dd falls below 4.0v (parameter d005 in electrical speci?ation section) for greater than param- eter #34 (see electrical speci?ation section), the brown-out situation will reset the chip. a reset may not occur if v dd falls below 4.0v for less than parameter #34. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will now be invoked and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above bv dd , the power-up timer will exe- cute a 72 ms time delay. the power-up timer should always be enabled when brown-out reset is enabled. figure 13-10 shows typical brown-out situations. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 13-10: brown-out situations 72 ms bv dd max. bv dd min. v dd internal reset bv dd max. bv dd min. v dd internal reset 72 ms <72 ms 72 ms bv dd max. bv dd min. v dd internal reset
pic16c6x ds30234d-page 130 1997 microchip technology inc. 13.4.5 time-out sequence on power-up the time-out sequence is as follows: first a pwrt time-out is invoked after the por time delay has expired. then ost is activated. the total time-out will vary based on oscillator con?uration and the sta- tus of the pwrt. for example, in rc mode, with the pwrt disabled, there will be no time-out at all. figure 13-11, figure 13-12, and figure 13-13 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if the m clr /v pp pin is kept low long enough, the time-outs will expire. then bringing the m clr /v pp pin high will begin execution immediately (figure 13-14). this is useful for testing purposes or to synchronize more than one pic16cxx device operating in parallel. table 13-10 and table 13-11 show the reset conditions for some special function registers, while table 13-12 shows the reset conditions for all the registers. 13.4.6 power control/status register (pcon) the power control/status register, pcon has up to two bits, depending upon the device. bit0 is not imple- mented on the pic16c62/64/65. bit0 is bo r (brown-out reset status bit). b o r is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bo r cleared, indicating that a brown-out has occurred. the bo r status bit is a ?on? care and is not necessarily predictable if the brown-out reset circuitry is disabled (by clearing bit boden in the con?uration word). bit1 is p or (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 table 13-5: time-out in various situations, pic16c61/62/64/65 table 13-6: time-out in various situations, pic16c62a/r62/63/r63/64a/r64/65a/r65/66/67 table 13-7: status bits and their significance, pic16c61 table 13-8: status bits and their significance, pic16c62/64/65 oscillator con?uration power-up wake-up from sleep pwrte = 1 pwrte = 0 xt, hs, lp 72 ms + 1024t osc 1024t osc 1024 t osc rc 72 ms oscillator con?uration power-up brown-out wake up from sleep pwr te = 0 pwr te = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024 t osc rc 72 ms 72 ms t o p d 11 power-on reset or mclr reset during normal operation 01 wdt reset 00 wdt wake-up 10 mclr reset during sleep or interrupt wake-up from sleep p or t o p d 011 power-on reset 00x illegal, t o is set on a power-on reset 0x0 illegal, pd is set on a power-on reset 101 wdt reset 100 wdt wake-up 1uu mclr reset during normal operation 110 mclr reset during sleep or interrupt wake-up from sleep legend: x = unknown, u = unchanged
1997 microchip technology inc. ds30234d-page 131 pic16c6x table 13-9: status bits and their significance for pic16c62a/r62/63/r63/64a/r64/65a/r65/66/67 table 13-10: reset condition for special registers on pic16c61/62/64/65 table 13-11: reset condition for special registers on pic16c62a/r62/63/r63/64a/r64/65a/r65/66/67 p or bo r t o p d 0x11 power-on reset 0x0x illegal, t o is set on a power-on reset 0xx0 illegal, pd is set on a power-on reset 10xx brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep legend: x = unknown, u = unchanged program counter status pcon (2) power-on reset 000h 0001 1xxx ---- --0- m clr reset during normal operation 000h 000u uuuu ---- --u- mclr reset during sleep 000h 0001 0uuu ---- --u- wdt reset 000h 0000 1uuu ---- --u- wdt wake-up pc + 1 uuu0 0uuu ---- --u- interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --u- legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the global enable bit, gie is set, the pc is loaded with the inter- rupt vector (0004h) after execution of pc+1. 2: the pcon register is not implemented on the pic16c61. program counter status pcon power-on reset 000h 0001 1xxx ---- --0x m clr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 wdt wake-up pc + 1 uuu0 0uuu ---- --uu interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and global enable bit, gie is set, the pc is loaded with the interrupt vector (0004h) after execution of pc+1.
pic16c6x ds30234d-page 132 1997 microchip technology inc. table 13-12: initialization conditions for all registers register applicable devices power-on reset brown-out reset m clr reset during: ?normal operation ?sleep wdt reset wake-up via interrupt or wdt wake-up w 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu indf 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 n/a n/a n/a tmr0 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu pcl 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000h 0000h pc + 1 (2) status 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu porta 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---x xxxx ---u uuuu ---u uuuu 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 --xx xxxx --uu uuuu --uu uuuu portb 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu portc 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu portd 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu porte 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---- -xxx ---- -uuu ---- -uuu pclath 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---0 0000 ---0 0000 ---u uuuu intcon 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 000x 0000 000u uuuu uuuu (1) pir1 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 00-- 0000 00-- 0000 uu-- uuuu (1) 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu (1) pir2 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---- ---0 ---- ---0 ---- ---u (2) tmr1l 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu t1con 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 --00 0000 --uu uuuu --uu uuuu tmr2 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu t2con 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 -000 0000 -000 0000 -uuu uuuu sspbuf 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu sspcon 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu ccpr1l 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 --00 0000 --00 0000 --uu uuuu rcsta 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 -00x 0000 -00x uuuu -uuu txreg 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu rcreg 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu ccpr2l 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu option 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 1111 1111 1111 1111 uuuu uuuu trisa 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---1 1111 ---1 1111 ---u uuuu 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 --11 1111 --11 1111 --uu uuuu trisb 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 1111 1111 1111 1111 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the global enable bit, gie is set, the pc is loaded with the interrupt vector (00 04h) after execution of pc + 1. 3: see table 13-10 and table 13-11 for reset value for speci? conditions.
1997 microchip technology inc. ds30234d-page 133 pic16c6x trisc 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 1111 1111 1111 1111 uuuu uuuu trisd 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 1111 1111 1111 1111 uuuu uuuu trise 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 -111 0000 -111 uuuu -uuu pie1 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 00-- 0000 00-- 0000 uu-- uuuu 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu pie2 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---- ---0 ---- ---0 ---- ---u pcon 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---- --0u ---- --uu ---- --uu 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 ---- --0- ---- --u- ---- --u- pr2 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 1111 1111 1111 1111 1111 1111 sspadd 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu sspstat 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 --00 0000 --00 0000 --uu uuuu txsta 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 -010 0000 -010 uuuu -uuu spbrg 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 0000 0000 0000 0000 uuuu uuuu table 13-12: initialization conditions for all registers (cont.d) register applicable devices power-on reset brown-out reset m clr reset during: ?normal operation ?sleep wdt reset wake-up via interrupt or wdt wake-up legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the global enable bit, gie is set, the pc is loaded with the interrupt vector (00 04h) after execution of pc + 1. 3: see table 13-10 and table 13-11 for reset value for speci? conditions.
pic16c6x ds30234d-page 134 1997 microchip technology inc. figure 13-11: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 13-12: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 13-13: time-out sequence on power-up (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset
1997 microchip technology inc. ds30234d-page 135 pic16c6x figure 13-14: external power-on reset circuit (for slow v dd power-up) note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the devices electrical speci?ations. 3: r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capacitor c in the event of mclr /v pp pin break- down due to electrostatic discharge (esd) or electrostatic overstress (eos). c r1 r d v dd mclr pic16cxx figure 13-15: external brown-out protection circuit 1 figure 13-16: external brown-out protection circuit 2 note 1: this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. 2: internal brown-out detection on the pic16c62a/r62/63/r63/64a/r64/65a/ r65/66/67 should be disabled when using this circuit. 3: resistors should be adjusted for the characteristics of the transistors. v dd 33k 10k 40k v dd mclr pic16cxx note 1: this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: internal brown-out detection on the pic16c62a/r62/63/r63/64a/r64/65a/ r65/66/67 should be disabled when using this circuit. 3: resistors should be adjusted for the characteristics of the transistors. v dd r1 r1 + r2 = 0.7v v dd r2 40k v dd mclr pic16cxx r1 q1
pic16c6x ds30234d-page 136 1997 microchip technology inc. 13.5 i nter rupts the pic16c6x family has up to 11 sources of interrupt. the interrupt control register (intcon) records individ- ual interrupt requests in ?g bits. it also has individual and global interrupt enable bits. global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupt ?g bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be disabled through their corresponding enable bits in the intcon register. gie is cleared on reset. the ?eturn from interrupt instruction, retfie , exits the interrupt routine as well as sets the gie bit, which re-enable interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 over?w interrupt ?g bits are contained in the intcon register. the peripheral interrupt ?g bits are contained in spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2 and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, bit gie is cleared to disable any further interrupts, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the rb0/int pin or rb port change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs (figure 13- 19). the latency is the same for one or two cycle instructions. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: individual interrupt ?g bits are set regard- less of the status of their corresponding mask bit or global enable bit, gie. avoid in?ite interrupt requests. individual interrupt ?g bits are set regardless of the status of their correspond- ing mask bit or the gie bit. note: for the pic16c61/62/64/65, if an interrupt occurs while the global interrupt enable bit, gie is being cleared, bit gie may unin- tentionally be re-enabled by the users interrupt service routine (the retfie instruction). the events that would cause this to occur are: 1. an instruction clears the gie bit while an interrupt is acknowledged 2. the program branches to the interrupt vector and executes the interrupt ser- vice routine. 3. the interrupt service routine com- pletes with the execution of the ret- fie instruction. this causes the gie bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to dis- able interrupts. 4. perform the following to ensure that interrupts are globally disabled. loop bcf intcon,gie ;disable global ;interrupt bit btfsc intcon,gie ;global interrupt ;disabled? goto loop ;no, try again : ;yes, continue ;with program flow
1997 microchip technology inc. ds30234d-page 137 pic16c6x figure 13-17: interrupt logic for pic16c61 figure 13-18: interrupt logic for pic16c6x rbif rbie t0if t0ie intf inte gie wake-up (if in sleep mode) interrupt to cpu tmr1if tmr1ie tmr2if tmr2ie ccp1if ccp1ie ccp2if ccp2ie txif txie rcif rcie sspif sspie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu pspie pspif the following table shows which devices have which interrupts. device t0if intf rbif pspif rcif txif sspif ccp1if tmr2if tmr1if ccp2if pic16c62 yes yes yes - - - yes yes yes yes - pic16c62a yes yes yes - - - yes yes yes yes - pic16cr62 yes yes yes - - - yes yes yes yes - pic16c63 yes yes yes - yes yes yes yes yes yes yes pic16cr63 yes yes yes - yes yes yes yes yes yes yes pic16c64 yes yes yes yes - - yes yes yes yes - pic16c64a yes yes yes yes - - yes yes yes yes - pic16c64 yes yes yes yes - - yes yes yes yes - pic16c65 yes yes yes yes yes yes yes yes yes yes yes pic16c65a yes yes yes yes yes yes yes yes yes yes yes pic16cr65 yes yes yes yes yes yes yes yes yes yes yes pic16c66 yes yes yes - yes yes yes yes yes yes yes pic16c67 yes yes yes yes yes yes yes yes yes yes yes
pic16c6x ds30234d-page 138 1997 microchip technology inc. 13.5.1 int interrupt external interrupt on rb0/int pin is edge triggered: either rising if edge select bit intedg (option<6>) is set, or falling, if bit intedg is clear. when a valid edge appears on the rb0/int pin, ?g bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). the intf bit must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake the processor from sleep, if enable bit inte was set prior to going into sleep. the status of global enable bit gie decides whether or not the processor branches to the interrupt vector following wake-up. see section 13.8 for details on sleep mode. 13.5.2 tmr0 interrupt an over?w (ffh ? 00h) in the tmr0 register will set ?g bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>) (section 7.0). 13.5.3 portb interrupt on change an input change on portb<7:4> sets ?g bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>) (section 5.2). note: for the pic16c61/62/64/65, if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then ?g bit rbif may not get set. figure 13-19: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout (3) int pin intf ?g (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instruction fetched instruction executed interrupt latency (2) pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) 1 4 5 1 note 1: intf ?g is sampled here (every q1). 2: interrupt latency = 3t cy for synchronous interrupt and 3-4t cy for asynchronous interrupt. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width spec of int pulse, refer to ac specs. 5: intf can to be set anytime during the q4-q1 cycles.
1997 microchip technology inc. ds30234d-page 139 pic16c6x 13.6 conte xt sa ving du ring interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt i.e., w register and status register. this will have to be implemented in software. example 13-1 stores and restores the status and w registers. example 13-2 stores and restores the status, w, and pclath registers (devices with paged program memory). for all pic16c6x devices with greater than 1k of program memory (all devices except pic16c61), the register, w_temp, must be de?ed in all banks and must be de?ed at the same offset from the bank base address (i.e., if w_temp is de?ed at 0x20 in bank 0, it must also be de?ed at 0xa0 in bank 1, 0x120 in bank 2, and 0x1a0 in bank 3). the examples: a) stores the w register b) stores the status register in bank 0 c) stores pclath d) executes isr code e) restores pclath f) restores status register (and bank select bit) g) restores w register applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 example 13-1: saving status and w registers in ram (pic16c61) movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w movwf status_temp ;save status to bank zero status_temp register : :(isr) : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w example 13-2: saving status, w, and pclath registers in ram (all other pic16c6x devices) movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page bcf status, irp ;return to bank 0 movf fsr, w ;copy fsr to w movwf fsr_temp ;copy fsr from w to fsr_temp :(isr) : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
pic16c6x ds30234d-page 140 1997 microchip technology inc. 13.7 w atc hdog tim er (wdt) the watchdog timer is a free running on-chip rc oscil- lator which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/ clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset. if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (wdt wake-up). the wdt can be perma- nently disabled by clearing con?uration bit wdte (section 13.1). 13.7.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). the time-out periods vary with tempera- ture, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 assigned to the wdt under software control by writing to the option register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset con- dition. the t o bit in the status register will be cleared upon a wdt time-out. 13.7.2 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt time-out occurs. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. figure 13-20: watchdog timer block diagram figure 13-21: summary of watchdog timer registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con?. bits (1) boden (1) cp1 cp0 pwrte (1) wdte fosc1 fosc0 81h,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see figure 13-1, figure 13-2, and figure 13-3 for details of these bits for the speci? device. from tmr0 clock source (see figure 7-6) to tmr0 (figure 7-6) watchdog timer wdt enable bit 0 1 m u x psa postscaler 8- to -1 mux ps2:ps0 01 mux psa wdt time-out 8 note: bits t0cs, t0se, psa, ps2:ps0 are (option<5:0>).
1997 microchip technology inc. ds30234d-page 141 pic16c6x 13.8 p o wer - d o wn mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, status bit p d (status<3>) is cleared, status bit t o (status<4>) is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd , or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, and disable external clocks. pull all i/o pins, that are hi-impedance inputs, high or low externally to avoid switching cur- rents caused by ?ating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr /v pp pin must be at a logic high level (v ihmc ). 13.8.1 wake-up from sleep the device can wake from sleep through one of the following events: 1. external reset input on mclr /v pp pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from rb0/int pin, rb port change, or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a ?ake-up? the t o and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up is cleared when sleep is invoked. the t o bit is cleared if wdt time-out occurred (and caused wake- up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ssp (start/stop) bit detect interrupt. 3. ssp transmit or receive in slave mode (spi/i 2 c). 4. ccp capture mode interrupt. 5. parallel slave port read or write. 6. usart tx or rx (synchronous slave mode). applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 other peripherals can not generate interrupts since during sleep, no on-chip q clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 13.8.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt ?g bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop. therefore, the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bits will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. even if the ?g bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop. to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic16c6x ds30234d-page 142 1997 microchip technology inc. figure 13-22: wake-up from sleep through interrupt note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake-up, the processor jumps to the interrupt routine. if gie = '0', execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf ?g (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 13.9 pr ogram v eri cation/code pr otection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for veri?ation purposes. 13.10 i d locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identi?ation numbers. these locations are not accessible during normal execution but are read- able and writable during program/verify. it is recom- mended that only the 4 least signi?ant bits of the id location are used. for rom devices, these values are submitted along with the rom code. 13.11 in-cir cuit serial pr og ramming the pic16cxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent ?mware or a custom ?m- ware to be programmed. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 note: microchip does not recommend code pro- tecting windowed devices. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 the device is placed into a program/verify mode by holding pins rb6 and rb7 low while raising the mclr (v pp ) pin from v il to v ihh (see programming speci?a- tion). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device in program/verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14-bits of program data are then sup- plied to or from the device, depending if the command was a load or a read. for complete details of serial pro- gramming, please refer to the pic16c6x/7x program- ming speci?ations (literature #ds30228). figure 13-23: typical in-circuit serial programming connection external connector signals to normal connections to normal connections pic16cxx v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
1997 microchip technology inc. ds30234d-page 143 pic16c6x 14.0 instruction set summary each pic16cxx instruction is a 14-bit word divided into an opcode which speci?s the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 14-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 14-1 shows the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e reg- ister designator and 'd' represents a destination desig- nator. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 14-1: opcode field descriptions field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in ?e register f. default is d = 1 label label name tos top of stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the speci?d register ?e location [ ] options ( ) contents ? assigned to < > register bit ?ld ? in the set of i talics user de?ed term (font is courier) the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 14-2 lists the instructions recognized by the mpasm assembler. figure 14-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. figure 14-1: general format for instructions note: to maintain upward compatibility with future pic16cxx products, do not use the option and tris instructions. byte-oriented ?e register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit ?e register address bit-oriented ?e register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit ?e register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c6x ds30234d-page 144 1997 microchip technology inc. table 14-2: pic16cxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z t o , pd z t o , pd c,dc,z z note 1: when an i/o register is modi?d as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigne d to the timer0 module. 3: if program counter (pc) is modi?d or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
1997 microchip technology inc. ds30234d-page 145 pic16c6x 14.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k ? (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example: addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d ? [0,1] operation: (w) + (f) ? (destination) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) ? (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal "k" process data write to w example andlw 0x5f before instruction w = 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .and. (f) ? (destination) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0 the result is stored in the w regis- ter. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02
pic16c6x ds30234d-page 146 1997 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 ? (f) status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 ? (f) status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '1' then the next instruction is executed. if bit 'b', in register 'f', is '0' then the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction . words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no- operation if skip: (2nd cycle) q1 q2 q3 q4 no- operation no- operation no- operation no- operation example here false true btfsc goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address true if flag<1>=1, pc = address false
1997 microchip technology inc. ds30234d-page 147 pic16c6x btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '0' then the next instruction is executed. if bit 'b' is '1', then the next instruction is discarded and a nop is executed instead, making this a 2t cy instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no- operation if skip: (2nd cycle) q1 q2 q3 q4 no- operation no- operation no- operation no- operation example here false true btfsc goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address false if flag<1> = 1, pc = address true call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read literal 'k', push pc to stack process data write to pc 2nd cycle no- operation no- operation no- operation no- operation example here call there before instruction pc = address here after instruction pc = address there tos = address here+1
pic16c6x ds30234d-page 148 1997 microchip technology inc. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h ? (f) 1 ? z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z encoding: 00 0001 0xxx xxxx description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no- operation process data write to w example clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? t o 1 ? pd status affected: t o , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits t o and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no- operation process data clear wdt counter example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler= 0 t o =1 pd =1
1997 microchip technology inc. ds30234d-page 149 pic16c6x comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d ? [0,1] operation: (f ) ? (destination) status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in w. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination) status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 1, the next instruction, is executed. if the result is 0, then a nop is executed instead making it a 2t cy instruc- tion. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: (2nd cycle) q1 q2 q3 q4 no- operation no- operation no- operation no- operation example here decfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt 1 0, pc = address here+1
pic16c6x ds30234d-page 150 1997 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read literal 'k' process data write to pc 2nd cycle no- operation no- operation no- operation no- operation example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination) status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1
1997 microchip technology inc. ds30234d-page 151 pic16c6x incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 1, the next instruction is executed. if the result is 0, a nop is executed instead making it a 2t cy instruction . words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: (2nd cycle) q1 q2 q3 q4 no- operation no- operation no- operation no- operation example here incfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 1 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k ? (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register is or?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example iorlw 0x35 before instruction w = 0x9a after instruction w = 0xbf z=1
pic16c6x ds30234d-page 152 1997 microchip technology inc. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .or. (f) ? (destination) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=1 movf move f syntax: [ label ] movf f,d operands: 0 f 127 d ? [0,1] operation: (f) ? (destination) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f is moved to a destination dependant upon the status of d. if d = 0, destination is w register. if d = 1, the destination is ?e register f itself. d = 1 is useful to test a ?e regis- ter since status ?g z is affected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example movf fsr, 0 after instruction w = value in fsr register z= 1 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register . the don? cares will assemble as 0s. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) ? (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register 'f' . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example movwf option_reg before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f
1997 microchip technology inc. ds30234d-page 153 pic16c6x nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no- operation no- operation no- operation example nop option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code com- patibility with pic16c5x products. since option is a readable/writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top of stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode no- operation set the gie bit pop from the stack 2nd cycle no- operation no- operation no- operation no- operation example retfie after interrupt pc = tos gie = 1
pic16c6x ds30234d-page 154 1997 microchip technology inc. retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode read literal 'k' no- operation write to w, pop from the stack 2nd cycle no- operation no- operation no- operation no- operation example table call table ;w contains table ;offset value ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 1st cycle decode no- operation no- operation pop from the stack 2nd cycle no- operation no- operation no- operation no- operation example return after interrupt pc = tos
1997 microchip technology inc. ds30234d-page 155 pic16c6x rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example rlf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 1100 1100 c =1 register f c rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example rrf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 0111 0011 c =0 register f c
pic16c6x ds30234d-page 156 1997 microchip technology inc. sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? t o , 0 ? pd status affected: t o , pd encoding: 00 0000 0110 0011 description: the power-down status bit, p d is cleared. time-out status bit, t o is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 13.8 for more details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no- operation no- operation go to sleep example: sleep sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ? ( w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2s comple- ment method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example 1: sublw 0x02 before instruction w= 1 c= ? z=? after instruction w= 1 c = 1; result is positive z=0 example 2: before instruction w= 2 c= ? z=? after instruction w= 0 c = 1; result is zero z=1 example 3: before instruction w= 3 c= ? z=? after instruction w = 0xff c = 0; result is negative z=0
1997 microchip technology inc. ds30234d-page 157 pic16c6x subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d ? [0,1] operation: (f) - (w) ? ( destination) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2s complement method) w reg- ister from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1: subwf reg1, 1 before instruction reg1 = 3 w=2 c=? z=? after instruction reg1 = 1 w=2 c = 1; result is positive z=0 example 2: before instruction reg1 = 2 w=2 c=? z=? after instruction reg1 = 0 w=2 c = 1; result is zero z=1 example 3: before instruction reg1 = 1 w=2 c=? z=? after instruction reg1 = 0xff w=2 c = 0; result is negative z=0 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d ? [0,1] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 f 7 operation: (w) ? tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x prod- ucts. since tris registers are read- able and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction.
pic16c6x ds30234d-page 158 1997 microchip technology inc. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?d with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to w example: xorlw 0xaf before instruction w = 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .xor. (f) ? ( destination) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example xorwf reg 1 before instruction reg = 0xaf w = 0xb5 after instruction reg = 0x1a w = 0xb5
1997 microchip technology inc. ds30234d-page 159 pic16c6x 15.0 development support 15.1 de velopme nt t ools the pic16/17 microcontrollers are supported with a full range of hardware and software development tools: picmaster/picmaster ce real-time in-circuit emulator icepic low-cost pic16c5x and pic16cxxx in-circuit emulator pro mate a ii universal programmer picstart a plus entry-level prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board picdem-3 low-cost demonstration board mpasm assembler mplab-sim software simulator mplab-c (c compiler) fuzzy logic development system ( fuzzy tech a - mp) 15.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic12c5xx, pic14c000, pic16c5x, pic16cxxx and pic17cxx families. picmaster is supplied with the mplab ? integrated development environment (ide), which allows editing, ?ake and download, and source debugging from a single environment. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new microchip micro- controllers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x environment were chosen to best make these fea- tures available to you, the end user. a ce compliant version of picmaster is available for european union (eu) countries. 15.3 i cepic: lo w-cost pic16cxxx in-cir cuit em ulator icepic is a low-cost in-circuit emulator solution for the microchip pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 286-at a through pentium ? based machines under windows 3.x environment. icepic features real time, non-intrusive emulation. 15.4 pr o ma te ii: univer sal pr ogrammer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic16c5x, pic16cxxx, pic17cxx and pic14000 devices. it can also set con?uration and code-protect bits in this mode. 15.5 p icst ar t plus entr y le vel de velopment system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming. picstart plus supports all pic12c5xx, pic14000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923 and pic16c924 may be supported with an adapter socket.
pic16c6x ds30234d-page 160 1997 microchip technology inc. 15.6 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate ii or picstart-16b programmer, and easily test ?m- ware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 15.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-16c, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 15.8 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test ?mware. the picmaster emulator may also be used with the picdem-3 board to test ?mware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals. 15.9 mplab integrated de velopment en vir onment softwar e the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or ?? one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e transfer data dynamically via dde (soon to be replaced by ole) run up to four emulators on the same pc the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 15.10 assemb ler (mp asm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from picmaster, microchips universal emulator system.
1997 microchip technology inc. ds30234d-page 161 pic16c6x mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic16/17. directives are helpful in making the development of your assemble source code shorter and more maintainable. 15.11 s oftware sim ulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the pic16/17 series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool. 15.12 c compiler ( mplab-c) the mplab-c code development system is a complete ? compiler and integrated development environment for microchips pic16/17 family of micro- controllers. the compiler provides powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display (picmaster emulator software versions 1.13 and later). 15.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 15.14 mp-drivew a y ? ?application code generator mp-driveway is an easy-to-use windows-based appli- cation code generator. with mp-driveway you can visually con?ure all the peripherals in a pic16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in c language. the output is fully compatible with micro- chips mplab-c c compiler. the code produced is highly modular and allows easy integration of your own code. mp-driveway is intelligent enough to maintain your code through subsequent code generation. 15.15 seev al a ev aluation and pr ogramming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can signi?antly reduce time-to-market and result in an optimized system. 15.16 t ruegaug e a intellig ent batter y mana g ement the truegauge development tool supports system development with the mta11200b truegauge intelli- gent battery management ic. system design veri?a- tion can be accomplished before hardware prototypes are built. user interface is graphically-oriented and measured data can be saved in a ?e for exporting to microsoft excel. 15.17 k ee l oq a ev aluation and pr ogramming t ools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
pic16c6x ds30234d-page 162 1997 microchip technology inc. table 15-1: development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c75x 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products picmaster a / picmaster-ce in-circuit emulator 444444444 available 3q97 icepic low-cost in-circuit emulator 4 44444 software tools mplab ? integrated development environment 444 4 444444 mplab ? c compiler 444 4 444444 fuzzy tech a -mp explorer/edition fuzzy logic dev. tool 444444444 mp-driveway ? applications code generator 44444 4 total endurance ? software model 4 programmers picstart a lite ultra low-cost dev. kit 4444 picstart a plus low-cost universal dev. kit 444 4 444444 pro mate a ii universal programmer 444 4 44444444 keeloq a programmer 4 demo boards seeval a designers kit 4 picdem-1 44 4 4 picdem-2 44 picdem-3 4 keeloq a evaluation kit 4
1997 microchip technology inc. ds30234d-page 163 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 16.0 electrical characteristics for pic16c61 absolute maximum ratings ? ambient temperature under bias................................................................................................. ............ .-55?c to +125?c storage temperature ............................................................................................................ ................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , m clr , and ra4) ..........................................-0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) .............................................................................................. 0v to +14v voltage on ra4 pin with respect to vss ......................................................................................... .................. 0v to +14v total power dissipation (note 1)............................................................................................... .............................800 mw maximum current out of v ss pin ........................................................................................................................... .150 ma maximum current into v dd pin ........................................................................................................................... ....100 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... ......................25 ma maximum output current sourced by any i/o pin .................................................................................. ...................20 ma maximum current sunk by porta .......................................................................................................................... .80 ma maximum current sourced by porta............................................................................................... .......................50 ma maximum current sunk by portb.................................................................................................. .......................150 ma maximum current sourced by portb ............................................................................................... ....................100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr pin rather than pulling this pin directly to v ss . table 16-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c61-04 pic16c61-20 pic16lc61-04 jw devices rc v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 1.0 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ. at 3.0v i pd : 0.6 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 1.0 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ. at 3.0v i pd : 0.6 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.0 m a typ. at 4.5v i pd : 1.0 m a typ. at 4.5v i pd : 1.0 m a typ. at 4.5v freq: 4 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 15 m a typ. at 32 khz, 4.0v i pd : 0.6 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode v dd : 3.0v to 6.0v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required.
pic16c6x ds30234d-page 164 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 16.1 dc characteristics: pic16c61-04 (commercial, industrial, extended) pic16c61-20 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power- on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d010 d013 supply current (note 2) i dd - - 1.8 13.5 3.3 30 ma ma f osc = 4 mhz, v dd = 5.5v (note 4) hs osc configuration f osc = 20 mhz, v dd = 5.5v d020 d021 d021a d021b power-down current (note 3) i pd - - - - 7 1.0 1.0 1.0 28 14 16 20 m a m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +125 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm.
1997 microchip technology inc. ds30234d-page 165 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 16.2 dc characteristics: pic16lc61-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v xt, rc, and lp osc con?uration d002* ram data retention volt- age (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d010 d010a supply current (note 2) i dd - - 1.4 15 2.5 32 ma m a f osc = 4 mhz, v dd = 3.0v (note 4) f osc = 32 khz, v dd = 3.0v, wdt disabled, lp osc con?uration d020 d021 d021a power-down current (note 3) i pd - - - 5 0.6 0.6 20 9 12 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm.
pic16c6x ds30234d-page 166 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 16.3 dc characteristics: pic16c61-04 (commercial, industrial, extended) pic16c61-20 (commercial, industrial, extended) pic16lc61-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 16.1 and section 16.2. param no. characteristic sym min typ? max units conditions input low voltage i/o ports v il d030 d030a with ttl buffer vss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer vss - 0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp) vss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.85v dd -v dd v for entire v dd range d042 mclr 0.85v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 ? 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c * the parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds30234d-page 167 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 output high voltage d090 i/o ports (note 3) v oh v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc con?) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* open-drain high voltage v od - - 14 v ra4 pin capacitive loading specs on output pins d100 osc2 pin c osc2 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io 50 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 16.1 and section 16.2. param no. characteristic sym min typ? max units conditions * the parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
pic16c6x ds30234d-page 168 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 16.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 16-1: load conditions for device timing specifications 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout 15 pf for osc2 output load condition 1 load condition 2
1997 microchip technology inc. ds30234d-page 169 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 16.5 t iming dia grams and speci cations figure 16-2: external clock timing table 16-2: external clock timing requirements parameter no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 1 4 mhz hs osc mode (-04) 1 20 mhz hs osc mode (-20) 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 1,000 ns hs osc mode (-04) 50 1,000 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 1.0 t cy dc m st cy = 4/fosc 3 tosl, tosh external clock in (osc1) high or low time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c6x ds30234d-page 170 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 16-3: clkout and i/o timing table 16-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 15 30 ns note 1 11* tosh2ckh osc1 - to clkout - 15 30 ns note 1 12* tckr clkout rise time 5 15 ns note 1 13* tckf clkout fall time 5 15 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 80 - 100 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20* tior port output rise time pic16 c 61 10 25 ns pic16 lc 61 60 ns 21* tiof port output fall time pic16 c 61 10 25 ns pic16 lc 61 60 ns 22??* tinp rb0/int pin high or low time 20 ns 23??* trbp rb7:rb4 change int high or low time 20 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value note: refer to figure 16-1 for load conditions.
1997 microchip technology inc. ds30234d-page 171 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 16-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 16-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 * tmcl mclr pulse width (low) 200 ns v dd = 5v, -40?c to +125?c 31 * twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33 * tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 * t ioz i/o hi-impedance from mclr low 100 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 16-1 for load conditions.
pic16c6x ds30234d-page 172 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 16-5: timer0 external clock timings table 16-5: timer0 external clock requirements parameter no. sym characteristic min typ? max units conditions 40 * tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41 * tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42 * tt0p t0cki period no prescaler t cy + 40 ns n = prescale value (2, 4, ..., 256) with prescaler greater of: 20 ns or t cy + 40 n ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 16-1 for load conditions. 41 42 40 ra4/t0cki tmr0
1997 microchip technology inc. ds30234d-page 173 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 17.0 dc and ac characteristics graphs and tables for pic16c61 the graphs and tables provided in this section are for design guidance and are not tested or guaranteed. in some graphs or tables the data presented are outside speci?d operating range (i.e., outside speci?d v dd range). this is for information only and devices are guaranteed to operate properly only within the speci?d range. note: the data presented in this section is a sta- tistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution while 'max' or 'min' represents (mean +3 s ) and (mean -3 s ) respectively where s is standard deviation. figure 17-1: typical rc oscillator frequency vs. temperature table 17-1: rc oscillator frequencies the percentage variation indicated here is part to part variation due to normal process distribution. the variation indi- cated is 3 standard deviation from average value for v dd = 5v. cext rext average fosc @ 5v, 25 c 20 pf 4.7k 4.52 mhz 17.35% 10k 2.47 mhz 10.10% 100k 290.86 khz 11.90% 100 pf 3.3k 1.92 mhz 9.43% 4.7k 1.48 mhz 9.83% 10k 788.77 khz 10.92% 100k 88.11 khz 16.03% 300 pf 3.3k 726.89 khz 10.97% 4.7k 573.95 khz 10.14% 10k 307.31 khz 10.43% 100k 33.82 khz 11.24% f osc f osc (25 c) 1.050 1.025 1.00 0.975 0.950 0.925 0.900 0.875 010 20253040506070 t ( c) frequency normalized t o +25 c v dd = 5.5v v dd = 3.5v r ext = 10 k w c ext = 100 pf 0.850
pic16c6x ds30234d-page 174 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-2: typical rc oscillator frequency vs. v dd figure 17-3: typical rc oscillator frequency vs. v dd 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 fosc (mhz) r = 10k r = 100k r = 4.7k cext = 20 pf, t = 25 c v dd (volts) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 fosc (mhz) r = 10k r = 4.7k r = 3.3k cext = 100 pf, t = 25 c r = 100k v dd (volts) figure 17-4: typical rc oscillator frequency vs. v dd figure 17-5: typical i pd vs. v dd watchdog timer disabled 25 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 fosc (mhz) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 r = 100k r = 10k r = 3.3k r = 4.7k cext = 300 pf, t = 25 c v dd (volts) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 175 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-6: typical i pd vs. v dd watchdog timer enabled 25 c 14 12 10 8 6 4 2 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) i pd ( m a) figure 17-7: maximum i pd vs. v dd watchdog disabled 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 0 c -55 c -40 c 70 c 85 c 125 c i pd ( m a) 25 20 15 10 5 0 data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 176 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-8: maximum i pd vs. v dd watchdog enabled* *i pd , with watchdog timer enabled, has two compo- nents: the leakage current which increases with higher temperature and the operating current of the watchdog timer logic which increases with lower temperature. at -40 c, the latter dominates explaining the apparently anomalous behavior. 45 3.0 -55 c 40 35 30 25 20 15 10 5 0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) i pd ( m a) -40 c 125 c 0 c 70 c 85 c figure 17-9: v th (input threshold voltage) of i/o pins vs. v dd v dd (volts) 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.60 max (-40 c to 85 c) v th (volts) 25 c, typ min (-40 c to 85 c) data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 177 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-10: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd figure 17-11: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v ih , max (-40 c to 85 c) v ih , min (-40 c to 85 c) v ih , typ (25 c) v ih , v il (volts) v il , max (-40 c to 85 c) v il , min (-40 c to 85 c) v il , typ (25 c) v dd (volts) these pins have schmitt trigger input buffers. 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 max (-40 c to 85 c) min (-40 c to 85 c) typ (25 c) v th (volts) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (volts) data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 178 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-12: typical i dd vs. frequency (external clock, 25 c) figure 17-13: maximum i dd vs. frequency (external clock, -40 to +85 c) 1 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) frequency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) frequency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 179 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-14: maximum i dd vs. frequency (external clock, -55 to +125 c) 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) frequency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 figure 17-15: wdt timer time-out period vs. v dd 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) max. 85 c max. 70 c typ. 25 c min. 0 c min. -40 c figure 17-16: transconductance (gm) of hs oscillator vs. v dd 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 234567 v dd (volts) gm ( m a/v) max. -40 c typ. 25 c min. 85 c data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 180 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-17: transconductance (gm) of lp oscillator vs. v dd figure 17-18: transconductance (gm) of xt oscillator vs. v dd 225 3.0 v dd (volts) gm ( m a/v) 200 175 150 125 100 75 50 25 0 3.5 4.0 4.5 5.0 5.5 6.0 max. -40 c typ. 25 c min. 85 c 2500 200 1500 100 500 0 234 567 v dd (volts) gm ( m a/v) max. -40 c typ. 25 c min. 85 c figure 17-19: i oh vs. v oh , v dd = 3v figure 17-20: i oh vs. v oh , v dd = 5v 0 -5 -10 -15 -20 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 v oh (volts) i oh (ma) max. -40 c typ. 25 c min. 85 c 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v oh (volts) i oh (ma) min @ 85 c typ @ 25 c max @ -40 c data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 181 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 17-21: i ol vs. v ol , v dd = 3v 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ol (volts) i ol (ma) min @ -40 c typ @ 25 c min @ +85 c figure 17-22: i ol vs. v ol , v dd = 5v min @ -40 c 80 90 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ol (volts) i ol (ma) min @ +85 c typ @ 25 c table 17-2: input capacitance* pin name typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1/clkin 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 *all capacitance values are typical at 25 c. a part to part variation of 25% (three standard deviations) should be taken into account. data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 182 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 notes:
1997 microchip technology inc. ds30234d-page 183 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 18.0 electrical characteristics for pic16c62/64 absolute maximum ratings ? ambient temperature under bias................................................................................................. .............. .-55?c to +85?c storage temperature ............................................................................................................ ................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , m clr , and ra4) ..........................................-0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ............................................................................................... 0v to +14v voltage on ra4 with respect to vss ............................................................................................ .................... 0v to +14v total power dissipation (note 1)............................................................................................... ..................................1.0w maximum current out of v ss pin ........................................................................................................................... .300 ma maximum current into v dd pin ........................................................................................................................... ....250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ......................25 ma maximum output current sourced by any i/o pin .................................................................................. ...................25 ma maximum current sunk by porta, portb, and porte* (combined) .................................................................200 ma maximum current sourced by porta, portb, and porte* (combined) ............................................................200 m a maximum current sunk by portc and portd* (combined)............................................................................ ....200 ma maximum current sourced by portc and portd* (combined) ......................................................................... .200 ma * portd and porte not available on the pic16c62. note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr pin rather than pulling this pin directly to v ss . table 18-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c62-04 pic16c64-04 pic16c62-10 pic16c64-10 pic16c62-20 pic16c64-20 pic16lc62-04 pic16lc64-04 jw devices rc v dd : 4.0v to 6.0v i dd : 3.8 ma max. at 5.5v i pd : 21 m a max. at 4v freq:4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq:4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq:4 mhz max. v dd : 3.0v to 6.0v i dd : 3.8 ma max. at 3.0v i pd : 13.5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.8 ma max. at 5.5v i pd : 21 m a max. at 4v freq:4 mhz max. xt v dd : 4.0v to 6.0v i dd : 3.8 ma max. at 5.5v i pd : 21 m a max. at 4v freq:4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq:4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq:4 mhz max. v dd : 3.0v to 6.0v i dd : 3.8 ma max. at 3.0v i pd : 13.5 m a max. at 3.0v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.8 ma max. at 5.5v i pd : 21 m a max. at 4v freq:4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 15 ma max. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq:4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq:200 khz max. not recommended for use in lp mode not recommended for use in lp mode v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 13.5 m a max. at 3.0v freq:200 khz max. v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd :13.5 m a max. at 3.0v freq:200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required.
pic16c6x ds30234d-page 184 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 18.1 dc characteristics: pic16c62/64-04 (commercial, industrial) pic16c62/64-10 (commercial, industrial) pic16c62/64-20 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power- on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d010 d013 supply current (note 2, 5) i dd - - 2.7 13.5 5.0 30 ma ma xt, rc, osc con?uration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con?uration f osc = 20 mhz, v dd = 5.5v d020 d021 d021a power-down current (note 3, 5) i pd - - - 10.5 1.5 1.5 42 21 24 m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested.
1997 microchip technology inc. ds30234d-page 185 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 18.2 dc characteristics: pic16lc62/64-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power- on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d010 d010a supply current (note 2, 5) i dd - - 2.0 22.5 3.8 48 ma m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021a power-down current (note 3, 5) i pd - - - 7.5 0.9 0.9 30 13.5 18 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested.
pic16c6x ds30234d-page 186 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 18.3 dc characteristics: pic16c62/64-04 (commercial, industrial) pic16c62/64-10 (commercial, industrial) pic16c62/64-20 (commercial, industrial) pic16lc62/64-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 18.1 and section 18.2 param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 d030a with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp) vss - 0.3v dd v note1 input high voltage i/o ports v ih d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 200 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c output high voltage d090 i/o ports (note 3) v oh v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc con?) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150* open-drain high voltage v od - - 14 v ra4 pin * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds30234d-page 187 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf d102 scl, sda in i 2 c mode cb - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 18.1 and section 18.2 param no. characteristic sym min typ ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as current sourced by the pin.
pic16c6x ds30234d-page 188 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 18.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 18-1: load conditions for device timing specifications 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2 note 1: portd and porte are not imple- mented on the pic16c62.
1997 microchip technology inc. ds30234d-page 189 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 18.5 t iming dia grams and speci cations figure 18-2: external clock timing table 18-2: external clock timing requirements parameter no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 100 ns hs osc mode (-10) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 100 250 ns hs osc mode (-10) 50 1,000 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 tosl, tosh external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c6x ds30234d-page 190 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-3: clkout and i/o timing table 18-3: clkout and i/o timing requirements parameters sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - t osc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c 62/64 100 ns pic16 lc 62/64 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0ns 20* tior port output rise time pic16 c 62/64 10 40 ns pic16 lc 62/64 80 ns 21* tiof port output fall time pic16 c 62/64 10 40 ns pic16 lc 62/64 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value note: refer to figure 18-1 for load conditions.
1997 microchip technology inc. ds30234d-page 191 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 18-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30* tmcl mclr pulse width (low) 100 ns v dd = 5v, -40?c to +85?c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +85?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40?c to +85?c 34* t ioz i/o hi-impedance from mclr low 100 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 18-1 for load conditions.
pic16c6x ds30234d-page 192 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-5: timer0 and timer1 external clock timings table 18-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 47* tt1p t1cki input period synchronous pic16 c 6x greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 6x greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16 c 6x 60 ns pic16 lc 6x 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ?200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-1 for load conditions. ra4/t0cki rc0/t1osi/t1cki tmr0 or tmr1 46 47 45 48 41 42 40
1997 microchip technology inc. ds30234d-page 193 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-6: capture/compare/pwm timings (ccp1) table 18-6: capture/compare/pwm requirements (ccp1) parameter no. sym characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 62/64 10 ns pic16 lc 62/64 20 ns 51* tcch ccp1 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 62/64 10 ns pic16 lc 62/64 20 ns 52* tccp ccp1 input period 3 t cy + 40 n ns n = prescale value (1,4 or 16) 53 tccr ccp1 output rise time pic16 c 62/64 ?025ns pic16 lc 62/64 ?545ns 54 tccf ccp1 output fall time pic16 c 62/64 ?025ns pic16 lc 62/64 ?545ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-1 for load conditions. rc2/ccp1 (capture mode) 50 51 52 rc2/ccp1 53 54 pwm mode) (compare or
pic16c6x ds30234d-page 194 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-7: parallel slave port timing (pic16c64) table 18-7: parallel slave port requirements (pic16c64) parameter no. sym characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63* twrh2dti wr - or cs - to data?n invalid (hold time) pic16 c 64 20 ns pic16 lc 64 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 65 trdh2dti rd - or cs - to data?ut invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1997 microchip technology inc. ds30234d-page 195 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-8: spi mode timing table 18-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) t cy + 20 ns 72 tscl sck input low time (slave mode) t cy + 20 ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 50 ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 50 ns 75 tdor sdo data output rise time 10 25 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) 10 25 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c6x ds30234d-page 196 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-9: i 2 c bus start/stop bits timing table 18-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: refer to figure 18-1 for load conditions scl sda start condition stop condition 90 91 92 93
1997 microchip technology inc. ds30234d-page 197 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 18-10: i 2 c bus data timing table 18-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 101 t low clock low time 100 khz mode 4.7 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. + tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 18-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c6x ds30234d-page 198 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 notes:
1997 microchip technology inc. ds30234d-page 199 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 19.0 electrical characteristics for pic16c62a/r62/64a/r64 absolute maximum ratings ? ambient temperature under bias................................................................................................. ............ .-55?c to +125?c storage temperature ............................................................................................................ ................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , m clr , and ra4) ..........................................-0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ............................................................................................... 0v to +14v voltage on ra4 with respect to vss ............................................................................................. .................... 0v to +14v total power dissipation (note 1)............................................................................................... ..................................1.0w maximum current out of v ss pin ........................................................................................................................... .300 ma maximum current into v dd pin ........................................................................................................................... ....250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ......................25 ma maximum output current sourced by any i/o pin .................................................................................. ...................25 ma maximum current sunk by porta, portb, and porte (combined)...................................................................200 ma maximum current sourced by porta, portb, and porte (combined) .............................................................200 m a maximum current sunk by portc and portd (combined) ............................................................................. ....200 ma maximum current sourced by portc and portd (combined).......................................................................... ..200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr pin rather than pulling this pin directly to v ss . table 19-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c62a-04 pic16cr62-04 pic16c64a-04 pic16cr64-04 pic16c62a-10 pic16cr62-10 pic16c64a-10 pic16cr64-10 pic16c62a-20 pic16cr62-20 pic16c64a-20 pic16cr64-20 pic16lc62a-04 pic16lcr62-04 pic16lc64a-04 pic16lcr64-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq:4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3.0v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq:4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.0 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3.0v i pd : 5 m a max. at 3.0v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 10 ma max. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode not recommended for use in lp mode v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required.
pic16c6x ds30234d-page 200 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 19.1 dc characteristics: pic16c62a/r62/64a/r64-04 (commercial, industrial, extended) pic16c62a/r62/64a/r64-10 (commercial, industrial, extended) pic16c62a/r62/64a/r64-20 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden bit in con?uration word enabled 3.7 4.0 4.4 v extended range only d010 d013 d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.7 10 350 5 20 425 ma ma m a xt, rc, osc con?uration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc configuration f osc = 20 mhz, v dd = 5.5v bor enabled, v dd = 5.0v d020 d021 d021a d021b d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - - 10.5 1.5 1.5 2.5 350 42 16 19 19 425 m a m a m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +125 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1997 microchip technology inc. ds30234d-page 201 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 19.2 dc characteristics: pic16lc62a/r62/64a/r64-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 2.5 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002* ram data retention volt- age (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden bit in con?uration word enabled d010 d010a d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.0 22.5 350 3.8 48 425 ma m a m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled bor enabled, v dd = 5.0v d020 d021 d021a d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - 7.5 0.9 0.9 350 30 5 5 425 m a m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c6x ds30234d-page 202 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 19.3 dc characteristics: pic16c62a/r62/64a/r64-04 (commercial, industrial, extended) pic16c62a/r62/64a/r64-10 (commercial, industrial, extended) pic16c62a/r62/64a/r64-20 (commercial, industrial, extended) pic16lc62a/r62/64a/r64-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 19.1 and section 19.2 param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 d030a with ttl buffer vss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer vss - 0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp) vss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi-imped- ance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds30234d-page 203 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 output high voltage d090 i/o ports (note 3) v oh v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc con?) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* open-drain high voltage v od - - 14 v ra4 pin capacitive loading specs on out- put pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf d102 scl, sda in i 2 c mode cb - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 19.1 and section 19.2 param no. characteristic sym min typ ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d lev- els represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as current sourced by the pin.
pic16c6x ds30234d-page 204 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 19.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 19-1: load conditions for device timing specifications 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2 note 1: portd and porte are not implemented on the pic16c62a/r62.
1997 microchip technology inc. ds30234d-page 205 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 19.5 t iming dia grams and speci cations figure 19-2: external clock timing table 19-2: external clock timing requirements parameter no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 100 ns hs osc mode (-10) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 100 250 ns hs osc mode (-10) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 tosl, tosh external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c6x ds30234d-page 206 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-3: clkout and i/o timing table 19-3: clkout and i/o timing requirements parameters sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c 62a/ r62/64a/r64 100 ns pic16 lc 62a/ r62/64a/r64 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16 c 62a/ r62/64a/r64 ?0 40 ns pic16 lc 62a/ r62/64a/r64 80 ns 21* tiof port output fall time pic16 c 62a/ r62/64a/r64 ?0 40 ns pic16 lc 62a/ r62/64a/r64 80 ns 22??* tinp rb0/int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value note: refer to figure 19-1 for load conditions.
1997 microchip technology inc. ds30234d-page 207 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 19-5: brown-out reset timing table 19-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m s v dd = 5v, -40?c to +125?c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m s v dd b vdd (param. d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 19-1 for load conditions. v dd bv dd 35
pic16c6x ds30234d-page 208 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-6: timer0 and timer1 external clock timings table 19-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 47* tt1p t1cki input period synchronous pic16 c 6x greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 6x greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16 c 6x 60 ns pic16 lc 6x 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ?200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 19-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
1997 microchip technology inc. ds30234d-page 209 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-7: capture/compare/pwm timings (ccp1) table 19-6: capture/compare/pwm requirements (ccp1) parameter no. sym characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 62a/r62/ 64a/r64 10 ns pic16 lc 62a/r62/ 64a/r64 20 ns 51* tcch ccp1 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 62a/r62/ 64a/r64 10 ns pic16 lc 62a/r62/ 64a/r64 20 ns 52* tccp ccp1 input period 3 t cy + 40 n ns n = prescale value (1,4 or 16) 53* tccr ccp1 output rise time pic16 c 62a/r62/ 64a/r64 ?025ns pic16 lc 62a/r62/ 64a/r64 ?545ns 54* tccf ccp1 output fall time pic16 c 62a/r62/ 64a/r64 ?025ns pic16 lc 62a/r62/ 64a/r64 ?545ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 19-1 for load conditions. rc2/ccp1 (capture mode) 50 51 52 rc2/ccp1 53 54 pwm mode) (compare or
pic16c6x ds30234d-page 210 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-8: parallel slave port timing (pic16c64a/r64) table 19-7: parallel slave port requirements (pic16c64a/r64) parameter no. sym characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 25 ns extended range only 63* twrh2dti wr - or cs - to data?n invalid (hold time) pic16 c 64a/r64 20 ns pic16 lc 64a/r64 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 90 ns extended range only 65* trdh2dti rd - or cs - to data?ut invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 19-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1997 microchip technology inc. ds30234d-page 211 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-9: spi mode timing table 19-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71* tsch sck input high time (slave mode) t cy + 20 ns 72* tscl sck input low time (slave mode) t cy + 20 ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 50 ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 50 ns 75* tdor sdo data output rise time 10 25 ns 76* tdof sdo data output fall time 10 25 ns 77* tssh2doz ss - to sdo output hi-impedance 10 50 ns 78* tscr sck output rise time (master mode) 10 25 ns 79* tscf sck output fall time (master mode) 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 19-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c6x ds30234d-page 212 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-10: i 2 c bus start/stop bits timing table 19-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93* t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 *these parameters are characterized but not tested. note: refer to figure 19-1 for load conditions scl sda start condition stop condition 90 91 92 93
1997 microchip technology inc. ds30234d-page 213 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 19-11: i 2 c bus data timing table 19-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 101* t low clock low time 100 khz mode 4.7 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91* t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107* t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109* t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 19-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c6x ds30234d-page 214 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 notes:
1997 microchip technology inc. ds30234d-page 215 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 20.0 electrical characteristics for pic16c65 absolute maximum ratings ? ambient temperature under bias................................................................................................. .............. .-55?c to +85?c storage temperature ............................................................................................................ ................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , m clr , and ra4) ..........................................-0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ............................................................................................... 0v to +14v voltage on ra4 with respect to vss ............................................................................................. .................... 0v to +14v total power dissipation (note 1)............................................................................................... ..................................1.0w maximum current out of v ss pin ........................................................................................................................... .300 ma maximum current into v dd pin ........................................................................................................................... ....250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ......................25 ma maximum output current sourced by any i/o pin .................................................................................. ...................25 ma maximum current sunk by porta, portb, and porte (combined)...................................................................200 ma maximum current sourced by porta, portb, and porte (combined) .............................................................200 m a maximum current sunk by portc and portd (combined) ............................................................................. ....200 ma maximum current sourced by portc and portd (combined).......................................................................... ..200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr pin rather than pulling this pin directly to v ss . table 20-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c65-04 pic16c65-10 pic16c65-20 pic16lc65-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 3.8 ma max. at 3v i pd : 800 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 3.8 ma max. at 3v i pd : 800 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 15 ma max. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd 1.0 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode not recommended for use in lp mode v dd : 3.0v to 6.0v i dd : 105 m a max. at 32 khz, 3.0v i pd : 800 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 105 m a max. at 32 khz, 3.0v i pd : 800 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recom- mended that the user select the device type that ensures the speci?ations required.
pic16c6x ds30234d-page 216 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 20.1 dc characteristics: pic16c65-04 (commercial, industrial) pic16c65-10 (commercial, industrial) pic16c65-20 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d010 d013 supply current (note 2, 5) i dd - - 2.7 13.5 5 30 ma ma xt, rc osc con?uration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con?uration f osc = 20 mhz, v dd = 5.5v d020 d021 d021a power-down current (note 3, 5) i pd - - - 10.5 1.5 1.5 800 800 800 m a m a m a v dd = 4.0v, wdt enabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-0 c to +70 c v dd = 4.0v, wdt disabled,-40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested.
1997 microchip technology inc. ds30234d-page 217 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 20.2 dc characteristics: pic16lc65-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d010 d010a supply current (note 2, 5) i dd - - 2.0 22.5 3.8 105 ma m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 4.0v, wdt disabled d020 d021 d021a power-down current (note 3, 5) i pd - - - 7.5 0.9 0.9 800 800 800 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested.
pic16c6x ds30234d-page 218 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 20.3 dc characteristics: pic16c65-04 (commercial, industrial) pic16c65-10 (commercial, industrial) pic16c65-20 (commercial, industrial) pic16lc65-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 20.1 and section 20.2 param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 d030a with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , osc1(in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp) vss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7 v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs, and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c output high voltage d090 i/o ports (note 3) v oh v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc con?) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150* open-drain high voltage v od - - 14 v ra4 pin * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds30234d-page 219 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf d102 scl, sda in i 2 c mode cb - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 20.1 and section 20.2 param no. characteristic sym min typ ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
pic16c6x ds30234d-page 220 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 20.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 20-1: load conditions for device timing specifications 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2
1997 microchip technology inc. ds30234d-page 221 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 20.5 t iming dia grams and speci cations figure 20-2: external clock timing table 20-2: external clock timing requirements parameter no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 100 ns hs osc mode (-10) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 100 250 ns hs osc mode (-10) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 tosl, tosh external clock in (osc1) high or low time 50 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c6x ds30234d-page 222 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-3: clkout and i/o timing table 20-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c 65 100 ns pic16 lc 65 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16 c 65 10 25 ns pic16 lc 65 60 ns 21* tiof port output fall time pic16 c 65 10 25 ns pic16 lc 65 60 ns 22??* tinp rb0/int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 20-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1997 microchip technology inc. ds30234d-page 223 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 20-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30* tmcl mclr pulse width (low) 100 ns v dd = 5v, -40?c to +85?c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +85?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33* tpwrt power-up timer period or wdt reset 28 72 132 ms v dd = 5v, -40?c to +85?c 34 t ioz i/o hi-impedance from mclr low 100 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 20-1 for load conditions.
pic16c6x ds30234d-page 224 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-5: timer0 and timer1 external clock timings table 20-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 47* tt1p t1cki input period synchronous pic16 c 6x greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 6x greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16 c 6x 60 ns pic16 lc 6x 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ?200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 20-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
1997 microchip technology inc. ds30234d-page 225 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-6: capture/compare/pwm timings (ccp1 and ccp2) table 20-6: capture/compare/pwm requirements (ccp1 and ccp2) parameter no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 65 10 ns pic16 lc 65 20 ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 65 10 ns pic16 lc 65 20 ns 52* tccp ccp1 and ccp2 input period 3 t cy + 40 n ns n = prescale value (1,4, or 16) 53 tccr ccp1 and ccp2 output rise time pic16 c 65 10 25 ns pic16 lc 65 25 45 ns 54 tccf ccp1 and ccp2 output fall time pic16 c 65 10 25 ns pic16 lc 65 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 20-1 for load conditions. rc1/t1osi/ccp2 and rc2/ccp1 (capture mode) 50 51 52 rc1/t1osi/ccp2 and rc2/ccp1 53 54 pwm mode) (compare or
pic16c6x ds30234d-page 226 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-7: parallel slave port timing table 20-7: parallel slave port requirements parameter no. sym characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63* twrh2dti wr - or cs - to data?n invalid (hold time) pic16 c 65 20 ns pic16 lc 65 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 65 trdh2dti rd - or cs - to data?ut invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 20-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1997 microchip technology inc. ds30234d-page 227 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-8: spi mode timing table 20-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) t cy + 20 ns 72 tscl sck input low time (slave mode) t cy + 20 ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 50 ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 50 ns 75 tdor sdo data output rise time 10 25 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) 10 25 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 20-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c6x ds30234d-page 228 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-9: i 2 c bus start/stop bits timing table 20-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: refer to figure 20-1 for load conditions 91 92 scl sda start condition stop condition 90 93
1997 microchip technology inc. ds30234d-page 229 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-10: i 2 c bus data timing table 20-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 0.6 m s devce must operate at a mini- mum of 10 mhz ssp module 1.5t cy 101 t low clock low time 100 khz mode 4.7 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 20-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c6x ds30234d-page 230 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 20-11: usart synchronous transmission (master/slave) timing table 20-11: usart synchronous transmission requirements figure 20-12: usart synchronous receive (master/slave) timing table 20-12: usart synchronous receive requirements parameter no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16 c 65 80 ns pic16 lc 65 100 ns 121 tckrf clock out rise time and fall time (master mode) pic16 c 65 45 ns pic16 lc 65 50 ns 122 tdtrf data out rise time and fall time pic16 c 65 45 ns pic16 lc 65 50 ns ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data setup before ck (dt setup time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 20-1 for load conditions 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 20-1 for load conditions 125 126 rc6/tx/ck rc7/rx/dt pin pin
1997 microchip technology inc. ds30234d-page 231 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 21.0 electrical characteristics for pic16c63/65a absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............ .-55?c to +125?c storage temperature ............................................................................................................ ................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , m clr , and ra4) ..........................................-0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ............................................................................................... 0v to +14v voltage on ra4 with respect to vss ............................................................................................. .................... 0v to +14v total power dissipation (note 1)............................................................................................... ..................................1.0w maximum current out of v ss pin ........................................................................................................................... .300 ma maximum current into v dd pin ........................................................................................................................... ....250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ......................25 ma maximum output current sourced by any i/o pin .................................................................................. ...................25 ma maximum current sunk by porta, portb, and porte (note 3) (combined).....................................................200 ma maximum current sourced by porta, portb, and porte (note 3) (combined) ...............................................200 ma maximum current sunk by portc and portd (note 3) (combined) ...................................................................200 ma maximum current sourced by portc and portd (note 3) (combined) ..............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr /v pp pin rather than pulling this pin directly to v ss . note 3: portd and porte not available on the pic16c63. table 21-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c63-04 pic16c65a-04 pic16c63-10 pic16c65a-10 pic16c63-20 pic16c65a-20 pic16lc63-04 pic16lc65a-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 10 ma max. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode not recommended for use in lp mode v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recom- mended that the user select the device type that ensures the speci?ations required.
pic16c6x ds30234d-page 232 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 21.1 dc characteristics: pic16c63/65a-04 (commercial, industrial, extended) pic16c63/65a-10 (commercial, industrial, extended) pic16c63/65a-20 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden con?uration bit is enabled 3.7 4.0 4.4 v extended range only d010 d013 d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.7 10 350 5 20 425 ma ma m a xt, rc, osc con? f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con? f osc = 20 mhz, v dd = 5.5v bor enabled, v dd = 5.0v d020 d021 d021a d021b d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - - 10.5 1.5 1.5 2.5 350 42 16 19 19 425 m a m a m a m a m a v dd = 4.0v, wdt enabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-0 c to +70 c v dd = 4.0v, wdt disabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-40 c to +125 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1997 microchip technology inc. ds30234d-page 233 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 21.2 dc characteristics: pic16lc63/65a-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 2.5 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden con?uration bit is enabled d010 d010a d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.0 22.5 350 3.8 48 425 ma m a m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled bor enabled, v dd = 5.0v d020 d021 d021a d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - 7.5 0.9 0.9 350 30 5 5 425 m a m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c6x ds30234d-page 234 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 21.3 dc characteristics: pic16c63/65a-04 (commercial, industrial, extended) pic16c63/65a-10 (commercial, industrial, extended) pic16c63/65a-20 (commercial, industrial, extended) pic16lc63/65a-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 21.1 and section 21.2 param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 d030a with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp) vss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds30234d-page 235 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 output high voltage d090 i/o ports (note 3) v oh v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc con?) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* open-drain high voltage v od - - 14 v ra4 pin capacitive loading specs on out- put pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf d102 scl, sda in i 2 c mode cb - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 21.1 and section 21.2 param no. characteristic sym min typ ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
pic16c6x ds30234d-page 236 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 21.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 21-1: load conditions for device timing specifications 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2 note 1: portd and porte are not imple- mented on the pic16c63.
1997 microchip technology inc. ds30234d-page 237 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 21.5 t iming dia grams and speci cations figure 21-2: external clock timing table 21-2: external clock timing requirements param no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 100 ns hs osc mode (-10) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 100 250 ns hs osc mode (-10) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3* tosl, tosh external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c6x ds30234d-page 238 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-3: clkout and i/o timing table 21-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c 63/65a 100 ns pic16 lc 63/65a 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16 c 63/65a 10 40 ns pic16 lc 63/65a 80 ns 21* tiof port output fall time pic16 c 63/65a 10 40 ns pic16 lc 63/65a 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 21-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1997 microchip technology inc. ds30234d-page 239 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 21-5: brown-out reset timing table 21-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m s v dd = 5v, -40?c to +125?c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m s v dd b vdd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 21-1 for load conditions. v dd bv dd 35
pic16c6x ds30234d-page 240 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-6: timer0 and timer1 external clock timings table 21-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 47* tt1p t1cki input period synchronous pic16 c 6x greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 6x greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16 c 6x 60 ns pic16 lc 6x 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ?200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
1997 microchip technology inc. ds30234d-page 241 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-7: capture/compare/pwm timings (ccp1 and ccp2) table 21-6: capture/compare/pwm requirements (ccp1 and ccp2) parameter no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 63/65a 10 ns pic16 lc 63/65a 20 ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 63/65a 10 ns pic16 lc 63/65a 20 ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ns n = prescale value (1,4, or 16) 53* tccr ccp1 and ccp2 output rise time pic16 c 63/65a 10 25 ns pic16 lc 63/65a 25 45 ns 54* tccf ccp1 and ccp2 output fall time pic16 c 63/65a 10 25 ns pic16 lc 63/65a 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions. rc1/t1osi/ccp2 and rc2/ccp1 (capture mode) 50 51 52 rc1/t1osi/ccp2 and rc2/ccp1 53 54 pwm mode) (compare or
pic16c6x ds30234d-page 242 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-8: parallel slave port timing (pic16c65a) table 21-7: parallel slave port requirements (pic16c65a) parameter no. sym characteristic min typ? max units conditions 62* tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 25 ns extended range only 63* twrh2dti wr - or cs - to data?n invalid (hold time) pic16 c 65a 20 ns pic16 lc 65a 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 90 ns extended range only 65* trdh2dti rd - or cs - to data?ut invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1997 microchip technology inc. ds30234d-page 243 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-9: spi mode timing table 21-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71* tsch sck input high time (slave mode) t cy + 20 ns 72* tscl sck input low time (slave mode) t cy + 20 ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 50 ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 50 ns 75* tdor sdo data output rise time 10 25 ns 76* tdof sdo data output fall time 10 25 ns 77* tssh2doz ss - to sdo output hi-impedance 10 50 ns 78* tscr sck output rise time (master mode) 10 25 ns 79* tscf sck output fall time (master mode) 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c6x ds30234d-page 244 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-10: i 2 c bus start/stop bits timing table 21-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 21-1 for load conditions 91 92 93 scl sda start condition stop condition 90
1997 microchip technology inc. ds30234d-page 245 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-11: i 2 c bus data timing table 21-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 101* t low clock low time 100 khz mode 4.7 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91* t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107* t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109* t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu:dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 21-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c6x ds30234d-page 246 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 21-12: usart synchronous transmission (master/slave) timing table 21-11: usart synchronous transmission requirements figure 21-13: usart synchronous receive (master/slave) timing table 21-12: usart synchronous receive requirements parameter no. sym characteristic min typ? max units conditions 120* tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16 c 63/65a 80 ns pic16 lc 63/65a 100 ns 121* tckrf clock out rise time and fall time (master mode) pic16 c 63/65a 45 ns pic16 lc 63/65a 50 ns 122* tdtrf data out rise time and fall time pic16 c 63/65a 45 ns pic16 lc 63/65a 50 ns * these parameters are characterized but not tested. ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125* tdtv2ckl sync rcv (master & sla ve) data setup before ck (dt setup time) 15 ns 126* tckl2dtl data hold after ck (dt hold time) 15 ns * these parameters are characterized but not tested. ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 21-1 for load conditions 125 126 rc6/tx/ck rc7/rx/dt pin pin
1997 microchip technology inc. preliminary ds30234d-page 247 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 22.0 electrical characteristics for pic16cr63/r65 absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............ .-55?c to +125?c storage temperature ............................................................................................................ ................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , m clr , and ra4) ..........................................-0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ............................................................................................... 0v to +14v voltage on ra4 with respect to vss ............................................................................................. .................... 0v to +14v total power dissipation (note 1)............................................................................................... ..................................1.0w maximum current out of v ss pin ........................................................................................................................... .300 ma maximum current into v dd pin ........................................................................................................................... ....250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ......................25 ma maximum output current sourced by any i/o pin .................................................................................. ...................25 ma maximum current sunk by porta, portb, and porte (note 3) (combined).....................................................200 ma maximum current sourced by porta, portb, and porte (note 3) (combined) ...............................................200 ma maximum current sunk by portc and portd (note 3) (combined) ...................................................................200 ma maximum current sourced by portc and portd (note 3) (combined) ..............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr /v pp pin rather than pulling this pin directly to v ss . note 3: portd and porte not available on the pic16cr63. table 22-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16cr63-04 pic16cr65-04 pic16cr63-10 pic16cr65-10 pic16cr63-20 pic16cr65-20 pic16lcr63-04 pic16lcr65-04 jw devices rc v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 5.5v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 5.5v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 10 ma max. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 5.5v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode not recommended for use in lp mode v dd : 3.0v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recom- mended that the user select the device type that ensures the speci?ations required.
pic16c6x ds30234d-page 248 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 22.1 dc characteristics: pic16cr63/r65-04 (commercial, industrial) pic16cr63/r65-10 (commercial, industrial) pic16cr63/r65-20 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 5.5 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden con?uration bit is enabled d010 d013 d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.7 10 350 5 20 425 ma ma m a xt, rc, osc con? f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con? f osc = 20 mhz, v dd = 5.5v bor enabled, v dd = 5.0v d020 d021 d021a d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - 10.5 1.5 1.5 350 42 16 19 425 m a m a m a m a v dd = 4.0v, wdt enabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-0 c to +70 c v dd = 4.0v, wdt disabled,-40 c to +85 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1997 microchip technology inc. preliminary ds30234d-page 249 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 22.2 dc characteristics: pic16lcr63/r65-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 5.5 v lp, xt, rc osc con?uration (dc - 4 mhz) d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden con?uration bit is enabled d010 d010a d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.0 22.5 350 3.8 48 425 ma m a m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled bor enabled, v dd = 5.0v d020 d021 d021a d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - 7.5 0.9 0.9 350 30 5 5 425 m a m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c6x ds30234d-page 250 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 22.3 dc characteristics: pic16cr63/r65-04 (commercial, industrial) pic16cr63/r65-10 (commercial, industrial) pic16cr63/r65-20 (commercial, industrial) pic16lcr63/r65-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 22.1 and section 22.2 param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 d030a with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp) vss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c output high voltage d090 i/o ports (note 3) v oh v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc con?) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150* open-drain high voltage v od - - 14 v ra4 pin * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. preliminary ds30234d-page 251 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 capacitive loading specs on out- put pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf d102 scl, sda in i 2 c mode cb - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 22.1 and section 22.2 param no. characteristic sym min typ ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
pic16c6x ds30234d-page 252 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 22.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 22-1: load conditions for device timing specifications 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2 note 1: portd and porte are not imple- mented on the pic16cr63.
1997 microchip technology inc. preliminary ds30234d-page 253 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 22.5 t iming dia grams and speci cations figure 22-2: external clock timing table 22-2: external clock timing requirements param no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 100 ns hs osc mode (-10) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 100 250 ns hs osc mode (-10) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3* tosl, tosh external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c6x ds30234d-page 254 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-3: clkout and i/o timing table 22-3: clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 cr 63/r65 100 ns pic16 lcr 63/r65 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16 cr 63/r65 10 40 ns pic16 lcr 63/r65 80 ns 21* tiof port output fall time pic16 cr 63/r65 10 40 ns pic16 lcr 63/r65 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 22-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1997 microchip technology inc. preliminary ds30234d-page 255 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 22-5: brown-out reset timing table 22-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m s v dd = 5v, -40?c to +125?c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m s v dd b vdd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 22-1 for load conditions. v dd bv dd 35
pic16c6x ds30234d-page 256 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-6: timer0 and timer1 external clock timings table 22-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 47* tt1p t1cki input period synchronous pic16 c 6x greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 6x greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16 c 6x 60 ns pic16 lc 6x 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ?200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 22-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
1997 microchip technology inc. preliminary ds30234d-page 257 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-7: capture/compare/pwm timings (ccp1 and ccp2) table 22-6: capture/compare/pwm requirements (ccp1 and ccp2) param no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 cr 63/r65 10 ns pic16 lcr 63/r65 20 ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 cr 63/r65 10 ns pic16 lcr 63/r65 20 ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ns n = prescale value (1,4, or 16) 53* tccr ccp1 and ccp2 output rise time pic16 cr 63/r65 10 25 ns pic16 lcr 63/r65 25 45 ns 54* tccf ccp1 and ccp2 output fall time pic16 cr 63/r65 10 25 ns pic16 lcr 63/r65 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 22-1 for load conditions. rc1/t1osi/ccp2 and rc2/ccp1 (capture mode) 50 51 52 rc1/t1osi/ccp2 and rc2/ccp1 53 54 pwm mode) (compare or
pic16c6x ds30234d-page 258 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-8: parallel slave port timing (pic16cr65) table 22-7: parallel slave port requirements (pic16cr65) parameter no. sym characteristic min typ? max units conditions 62* tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63* twrh2dti wr - or cs - to data?n invalid (hold time) pic16 cr 65 20 ns pic16 lcr 65 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 65* trdh2dti rd - or cs - to data?ut invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 22-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1997 microchip technology inc. preliminary ds30234d-page 259 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-9: spi mode timing table 22-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71* tsch sck input high time (slave mode) t cy + 20 ns 72* tscl sck input low time (slave mode) t cy + 20 ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 50 ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 50 ns 75* tdor sdo data output rise time 10 25 ns 76* tdof sdo data output fall time 10 25 ns 77* tssh2doz ss - to sdo output hi-impedance 10 50 ns 78* tscr sck output rise time (master mode) 10 25 ns 79* tscf sck output fall time (master mode) 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 22-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c6x ds30234d-page 260 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-10: i 2 c bus start/stop bits timing table 22-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 22-1 for load conditions 91 92 93 scl sda start condition stop condition 90
1997 microchip technology inc. preliminary ds30234d-page 261 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-11: i 2 c bus data timing table 22-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 101* t low clock low time 100 khz mode 4.7 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91* t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107* t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109* t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu:dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 22-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c6x ds30234d-page 262 preliminary 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 22-12: usart synchronous transmission (master/slave) timing table 22-11: usart synchronous transmission requirements figure 22-13: usart synchronous receive (master/slave) timing table 22-12: usart synchronous receive requirements param no. sym characteristic min typ? max units conditions 120* tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16 cr 63/r65 80 ns pic16 lcr 63/r65 100 ns 121* tckrf clock out rise time and fall time (master mode) pic16 cr 63/r65 45 ns pic16 lcr 63/r65 50 ns 122* tdtrf data out rise time and fall time pic16 cr 63/r65 45 ns pic16 lcr 63/r65 50 ns * these parameters are characterized but not tested. ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125* tdtv2ckl sync rcv (master & sla ve) data setup before ck (dt setup time) 15 ns 126* tckl2dtl data hold after ck (dt hold time) 15 ns * these parameters are characterized but not tested. ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 22-1 for load conditions 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 22-1 for load conditions 125 126 rc6/tx/ck rc7/rx/dt pin pin
1997 microchip technology inc. ds30234d-page 263 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 23.0 electrical characteristics for pic16c66/67 absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............ .-55?c to +125?c storage temperature ............................................................................................................ ................... -65?c to +150?c voltage on any pin with respect to v ss (except v dd , m clr , and ra4) ..........................................-0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss .......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ............................................................................................... 0v to +14v voltage on ra4 with respect to vss ............................................................................................. .................... 0v to +14v total power dissipation (note 1)............................................................................................... ..................................1.0w maximum current out of v ss pin ........................................................................................................................... .300 ma maximum current into v dd pin ........................................................................................................................... ....250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ......................25 ma maximum output current sourced by any i/o pin .................................................................................. ...................25 ma maximum current sunk by porta, portb, and porte (note 3) (combined).....................................................200 ma maximum current sourced by porta, portb, and porte (note 3) (combined) ...............................................200 ma maximum current sunk by portc and portd (note 3) (combined) ...................................................................200 ma maximum current sourced by portc and portd (note 3) (combined) ..............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr /v pp pin rather than pulling this pin directly to v ss . note 3: portd and porte not available on the pic16c66. table 23-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c66-04 pic16c67-04 pic16c66-10 pic16c67-10 pic16c66-20 pic16c67-20 pic16lc66-04 pic16lc67-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 6.0v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 10 ma max. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode not recommended for use in lp mode v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. v dd : 2.5v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recom- mended that the user select the device type that ensures the speci?ations required.
pic16c6x ds30234d-page 264 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 23.1 dc characteristics: pic16c66/67-04 (commercial, industrial, extended) pic16c66/67-10 (commercial, industrial, extended) pic16c66/67-20 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden con?uration bit is enabled 3.7 4.0 4.4 v extended range only d010 d013 d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.7 10 350 5 20 425 ma ma m a xt, rc, osc con? f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con? f osc = 20 mhz, v dd = 5.5v bor enabled, v dd = 5.0v d020 d021 d021a d021b d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - - 10.5 1.5 1.5 2.5 350 42 16 19 19 425 m a m a m a m a m a v dd = 4.0v, wdt enabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-0 c to +70 c v dd = 4.0v, wdt disabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-40 c to +125 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1997 microchip technology inc. ds30234d-page 265 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 23.2 dc characteristics: pic16lc66/67-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 2.5 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002* ram data retention voltage (note 1) v dr - 1.5 - v d003 v dd start voltage to ensure internal power-on reset signal v por -v ss - v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 - - v/ms see section on power-on reset for details d005 brown-out reset voltage b vdd 3.7 4.0 4.3 v boden con?uration bit is enabled d010 d010a d015* supply current (note 2, 5) brown-out reset current (note 6) i dd d i bor - - - 2.0 22.5 350 3.8 48 425 ma m a m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled bor enabled, v dd = 5.0v d020 d021 d021a d023* power-down current (note 3, 5) brown-out reset current (note 6) i pd d i bor - - - - 7.5 0.9 0.9 350 30 5 5 425 m a m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c bor enabled, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from character- ization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c6x ds30234d-page 266 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 23.3 dc characteristics: pic16c66/67-04 (commercial, industrial, extended) pic16c66/67-10 (commercial, industrial, extended) pic16c66/67-20 (commercial, industrial, extended) pic16lc66/67-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 23.1 and section 23.2 param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 d030a with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp) vss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
1997 microchip technology inc. ds30234d-page 267 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 output high voltage d090 i/o ports (note 3) v oh v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc con?) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* open-drain high voltage v od - - 14 v ra4 pin capacitive loading specs on out- put pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf d102 scl, sda in i 2 c mode cb - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for extended, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 23.1 and section 23.2 param no. characteristic sym min typ ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c6x be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
pic16c6x ds30234d-page 268 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 23.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 23-1: load conditions for device timing specifications 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2 note 1: portd and porte are not imple- mented on the pic16c66.
1997 microchip technology inc. ds30234d-page 269 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 23.5 t iming dia grams and speci cations figure 23-2: external clock timing table 23-2: external clock timing requirements param no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 10 mhz hs osc mode (-10) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 100 ns hs osc mode (-10) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 100 250 ns hs osc mode (-10) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3* tosl, tosh external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c6x ds30234d-page 270 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-3: clkout and i/o timing table 23-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c 66/67 100 ns pic16 lc 66/67 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16 c 66/67 10 40 ns pic16 lc 66/67 80 ns 21* tiof port output fall time pic16 c 66/67 10 40 ns pic16 lc 66/67 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 23-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1997 microchip technology inc. ds30234d-page 271 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 23-5: brown-out reset timing table 23-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m s v dd = 5v, -40?c to +125?c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m s v dd b vdd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 23-1 for load conditions. v dd bv dd 35
pic16c6x ds30234d-page 272 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-6: timer0 and timer1 external clock timings table 23-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 6x 15 ns pic16 lc 6x 25 ns asynchronous pic16 c 6x 30 ns pic16 lc 6x 50 ns 47* tt1p t1cki input period synchronous pic16 c 6x greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 6x greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16 c 6x 60 ns pic16 lc 6x 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ?200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
1997 microchip technology inc. ds30234d-page 273 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-7: capture/compare/pwm timings (ccp1 and ccp2) table 23-6: capture/compare/pwm requirements (ccp1 and ccp2) parameter no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 66/67 10 ns pic16 lc 66/67 20 ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 66/67 10 ns pic16 lc 66/67 20 ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ns n = prescale value (1,4, or 16) 53* tccr ccp1 and ccp2 output rise time pic16 c 66/67 10 25 ns pic16 lc 66/67 25 45 ns 54* tccf ccp1 and ccp2 output fall time pic16 c 66/67 10 25 ns pic16 lc 66/67 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions. rc1/t1osi/ccp2 and rc2/ccp1 (capture mode) 50 51 52 rc1/t1osi/ccp2 and rc2/ccp1 53 54 pwm mode) (compare or
pic16c6x ds30234d-page 274 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-8: parallel slave port timing (pic16c67) table 23-7: parallel slave port requirements (pic16c67) parameter no. sym characteristic min typ? max units conditions 62* tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 25 ns extended range only 63* twrh2dti wr - or cs - to data?n invalid (hold time) pic16 c 67 20 ns pic16 lc 67 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 90 ns extended range only 65* trdh2dti rd - or cs - to data?ut invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1997 microchip technology inc. ds30234d-page 275 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-9: spi master mode timing (cke = 0) figure 23-10: spi master mode timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 refer to figure 23-1 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb refer to figure 23-1 for load conditions.
pic16c6x ds30234d-page 276 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-11: spi slave mode timing (cke = 0) figure 23-12: spi slave mode timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 refer to figure 23-1 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 refer to figure 23-1 for load conditions.
1997 microchip technology inc. ds30234d-page 277 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 table 23-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70* tssl2sch, tssl2scl s s to sck or sck - input t cy ns 71* tsch sck input high time (slave mode) t cy + 20 ns 72* tscl sck input low time (slave mode) t cy + 20 ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 74* tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75* tdor sdo data output rise time 10 25 ns 76* tdof sdo data output fall time 10 25 ns 77* tssh2doz ss - to sdo output hi-impedance 10 50 ns 78* tscr sck output rise time (master mode) 10 25 ns 79* tscf sck output fall time (master mode) 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns 81* tdov2sch, tdov2scl sdo data output setup to sck edge t cy ns 82* tssl2dov sdo data output valid after ss edge 50 ns 83* tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c6x ds30234d-page 278 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-13: i 2 c bus start/stop bits timing table 23-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 23-1 for load conditions 91 92 93 scl sda start condition stop condition 90
1997 microchip technology inc. ds30234d-page 279 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-14: i 2 c bus data timing table 23-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 101* t low clock low time 100 khz mode 4.7 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91* t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107* t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109* t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu:dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 23-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c6x ds30234d-page 280 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 23-15: usart synchronous transmission (master/slave) timing table 23-11: usart synchronous transmission requirements figure 23-16: usart synchronous receive (master/slave) timing table 23-12: usart synchronous receive requirements parameter no. sym characteristic min typ? max units conditions 120* tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16 c 66/67 80 ns pic16 lc 66/67 100 ns 121* tckrf clock out rise time and fall time (master mode) pic16 c 66/67 45 ns pic16 lc 66/67 50 ns 122* tdtrf data out rise time and fall time pic16 c 66/67 45 ns pic16 lc 66/67 50 ns * these parameters are characterized but not tested. ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125* tdtv2ckl sync rcv (master & sla ve) data setup before ck (dt setup time) 15 ns 126* tckl2dtl data hold after ck (dt hold time) 15 ns * these parameters are characterized but not tested. ?: data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 23-1 for load conditions 125 126 rc6/tx/ck rc7/rx/dt pin pin
1997 microchip technology inc. ds30234d-page 281 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 24.0 dc and ac characteristics graphs and tables for: pic16c62, pic16c62a, pic16cr62, pic16c63, pic16c64, pic16c64a, pic16cr64, pic16c65a, pic16c66, pic16c67 the graphs and tables provided in this section are for design guidance and are not tested or guaranteed. in some graphs or tables the data presented are outside speci?d operating range (i.e., outside speci?d v dd range). this is for information only and devices are guaranteed to operate properly only within the speci?d range. figure 24-1: typical i pd vs. v dd (wdt disabled, rc mode) figure 24-2: maximum i pd vs. v dd (wdt disabled, rc mode) note: the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at, 25 c, while 'max' or 'min' represents (mean +3 s ) and (mean -3 s ) respectively where s is standard deviation. 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) i pd ( m a) v dd (volts) 10.000 1.000 0.100 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 85 c 70 c 25 c 0 c -40 c
pic16c6x ds30234d-page 282 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-3: typical i pd vs. v dd @ 25 c (wdt enabled, rc mode) figure 24-4: maximum i pd vs. v dd (wdt enabled, rc mode) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 35 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) -40 c 0 c 70 c 85 c figure 24-5: typical rc oscillator frequency vs. v dd figure 24-6: typical rc oscillator frequency vs. v dd figure 24-7: typical rc oscillator frequency vs. v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 fosc(mhz) cext = 22 pf, t = 25 c r = 100k r = 10k r = 5k shaded area is beyond recommended range. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 fosc(mhz) cext = 100 pf, t = 25 c r = 100k r = 10k r = 5k r = 3.3k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 1000 900 800 700 600 500 400 300 200 100 0 fosc(khz) cext = 300 pf, t = 25 c r = 3.3k r = 5k r = 10k r = 100k data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 283 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-8: typical i pd vs. v dd brown- out detect enabled (rc mode) figure 24-9: maximum i pd vs. v dd brown-out detect enabled (85 c to -40 c, rc mode) the shaded region represents the built-in hysteresis of the brown-out reset circuitry. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (volts) i pd ( m a) device in brown-out device not in brown-out reset reset the shaded region represents the built-in hysteresis of the brown-out reset circuitry. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1400 1200 1000 800 600 400 200 0 v dd (volts) i pd ( m a) 4.3 1600 device not in brown-out reset device in brown-out reset figure 24-10: typical i pd vs. timer1 enabled (32 khz, rc0/rc1 = 33 pf/33 pf, rc mode) figure 24-11: maximum i pd vs. timer1 enabled (32 khz, rc0/rc1 = 33 pf/33 pf, 85 c to -40 c, rc mode) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) i pd ( m a) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) i pd ( m a) 35 40 45 data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 284 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-12: typical i dd vs. frequency (rc mode @ 22 pf, 25 c) figure 24-13: maximum i dd vs. frequency (rc mode @ 22 pf, -40 c to 85 c) 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 frequency(mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v beyond recommended range 2000 1800 1600 1400 1200 800 1000 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 frequency(mhz) i dd ( m a) shaded area is 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v beyond recommended range data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 285 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-14: typical i dd vs. frequency (rc mode @ 100 pf, 25 c) figure 24-15: maximum i dd vs. frequency (rc mode @ 100 pf, -40 c to 85 c) 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 frequency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is beyond recommended range 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 frequency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v shaded area is beyond recommended range data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 286 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-16: typical i dd vs. frequency (rc mode @ 300 pf, 25 c) figure 24-17: maximum i dd vs. frequency (rc mode @ 300 pf, -40 c to 85 c) 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 frequency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 frequency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 287 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-18: typical i dd vs. capacitance @ 500 khz (rc mode) table 24-1: rc oscillator frequencies cext rext average fosc @ 5v, 25 c 22 pf 5k 4.12 mhz 1.4% 10k 2.35 mhz 1.4% 100k 268 khz 1.1% 100 pf 3.3k 1.80 mhz 1.0% 5k 1.27 mhz 1.0% 10k 688 khz 1.2% 100k 77.2 khz 1.0% 300 pf 3.3k 707 khz 1.4% 5k 501 khz 1.2% 10k 269 khz 1.6% 100k 28.3 khz 1.1% the percentage variation indicated here is part to part variation due to normal process distribution. the variation indicated is 3 standard deviation from average value for v dd = 5v. capacitance(pf) 600 i dd ( m a) 500 400 300 200 100 0 20 pf 100 pf 300 pf 5.0v 4.0v 3.0v figure 24-19: transconductance(gm) of hs oscillator vs. v dd figure 24-20: transconductance(gm) of lp oscillator vs. v dd figure 24-21: transconductance(gm) of xt oscillator vs. v dd 4.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (volts) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 max -40 c typ 25 c min 85 c shaded area is beyond recommended range 110 100 90 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (volts) max -40 c typ 25 c min 85 c shaded areas are beyond recommended range 1000 900 800 700 600 500 400 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 gm( m a/v) v dd (volts) max -40 c typ 25 c min 85 c shaded areas are beyond recommended range data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 288 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-22: typical xtal startup time vs. v dd (lp mode, 25 c) figure 24-23: typical xtal startup time vs. v dd (hs mode, 25 c) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) startup time(seconds) 32 khz, 33 pf/33 pf 200 khz, 15 pf/15 pf 7 6 5 4 3 2 1 4.0 4.5 5.0 5.5 6.0 v dd (volts) startup time(ms) 20 mhz, 33 pf/33 pf 8 mhz, 33 pf/33 pf 8 mhz, 15 pf/15 pf 20 mhz, 15 pf/15 pf figure 24-24: typical xtal startup time vs. v dd (xt mode, 25 c) table 24-2: capacitor selection for crystal oscillators osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm 70 60 50 40 30 20 10 0 3.0 3.5 2.5 4.0 5.0 5.5 6.0 4.5 v dd (volts) startup time(ms) 200 khz, 68 pf/68 pf 200 khz, 47 pf/47 pf 1 mhz, 15 pf/15 pf 4 mhz, 15 pf/15 pf data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 289 pic16c6x applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-25: typical i dd vs. frequency (lp mode, 25 c) figure 24-26: maximum i dd vs. frequency (lp mode, 85 c to -40 c) 120 100 80 60 40 20 0 0 50 100 150 200 frequency(khz) i dd ( m a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 120 100 80 60 40 20 0 0 50 100 150 200 frequency(khz) i dd ( m a) 140 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v figure 24-27: typical i dd vs. frequency (xt mode, 25 c) figure 24-28: maximum i dd vs. frequency (xt mode, -40 c to 85 c) 1200 1000 800 600 400 200 0 0.0 0.4 frequency(mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 1200 1000 800 600 400 200 0 0.0 0.4 frequency(mhz) i dd ( m a) 1400 1600 1800 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v data based on matrix samples. see rst page of this section for details.
pic16c6x ds30234d-page 290 1997 microchip technology inc. applicable devices 61 62 62a r62 63 r63 64 64a r64 65 65a r65 66 67 figure 24-29: typical i dd vs. frequency (hs mode, 25 c) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 12 4 6 8 10 12 14 16 18 20 frequency(mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v figure 24-30: maximum i dd vs. frequency (hs mode, -40 c to 85 c) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 12 4 6 8 10 12 14 16 18 20 frequency(mhz) i dd (ma) 6.0v 5.5v 5.0v 4.5v 4.0v data based on matrix samples. see rst page of this section for details.
1997 microchip technology inc. ds30234d-page 291 pic16c6x 25.0 packaging information 25.1 18-lead plastic dual in-line (300 mil) (p) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.064 0.160 a1 0.381 0.015 a2 3.048 3.810 0.120 0.150 b 0.355 0.559 0.014 0.022 b1 1.524 1.524 reference 0.060 0.060 reference c 0.203 0.381 typical 0.008 0.015 typical d 22.479 23.495 0.885 0.925 d1 20.320 20.320 reference 0.800 0.800 reference e 7.620 8.255 0.300 0.325 e1 6.096 7.112 0.240 0.280 e1 2.489 2.591 typical 0.098 0.102 typical ea 7.620 7.620 reference 0.300 0.300 reference eb 7.874 9.906 0.310 0.390 l 3.048 3.556 0.120 0.140 n 1818 1818 s 0.889 0.035 s1 0.127 0.005 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
pic16c6x ds30234d-page 292 1997 microchip technology inc. 25.2 28-lead plastic dual in-line (300 mil) (sp) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.632 4.572 0.143 0.180 a1 0.381 0.015 a2 3.175 3.556 0.125 0.140 b 0.406 0.559 0.016 0.022 b1 1.016 1.651 typical 0.040 0.065 typical b2 0.762 1.016 4 places 0.030 0.040 4 places b3 0.203 0.508 4 places 0.008 0.020 4 places c 0.203 0.331 typical 0.008 0.013 typical d 34.163 35.179 1.385 1.395 d1 33.020 33.020 reference 1.300 1.300 reference e 7.874 8.382 0.310 0.330 e1 7.112 7.493 0.280 0.295 e1 2.540 2.540 typical 0.100 0.100 typical ea 7.874 7.874 reference 0.310 0.310 reference eb 8.128 9.652 0.320 0.380 l 3.175 3.683 0.125 0.145 n 2828 2828 s 0.584 1.220 0.023 0.048 n pin no. 1 indicator area e1 e s d d1 base plane seating plane a1 a2 a l e1 a c e a e b detail a detail a b2 b1 b b3
1997 microchip technology inc. ds30234d-page 293 pic16c6x 25.3 40-lead plastic dual in-line (600 mil) (p) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.381 0.015 a2 3.175 4.064 0.125 0.160 b 0.355 0.559 0.014 0.022 b1 1.270 1.778 typical 0.050 0.070 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.181 52.197 2.015 2.055 d1 48.260 48.260 reference 1.900 1.900 reference e 15.240 15.875 0.600 0.625 e1 13.462 13.970 0.530 0.550 e1 2.489 2.591 typical 0.098 0.102 typical ea 15.240 15.240 reference 0.600 0.600 reference eb 15.240 17.272 0.600 0.680 l 2.921 3.683 0.115 0.145 n 4040 4040 s 1.270 0.050 s1 0.508 0.020 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
pic16c6x ds30234d-page 294 1997 microchip technology inc. 25.4 18-lead plastic surface mount (soic - wide , 300 mil bod y) (so) package group: plastic soic (so) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 11.353 11.735 0.447 0.462 e 7.416 7.595 0.292 0.299 e 1.270 1.270 reference 0.050 0.050 reference h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 n 1818 1818 cp 0.102 0.004 b e n index area chamfer h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
1997 microchip technology inc. ds30234d-page 295 pic16c6x 25.5 28-lead plastic surface mount (soic - wide , 300 mil bod y) (so) package group: plastic soic (so) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 17.703 18.085 0.697 0.712 e 7.416 7.595 0.292 0.299 e 1.270 1.270 typical 0.050 0.050 typical h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 n 2828 2828 cp 0.102 0.004 b e n index area chamfer h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
pic16c6x ds30234d-page 296 1997 microchip technology inc. 25.6 18-lead ceramic cerdip dual in-line with windo w (300 mil) (jw) package group: ceramic cerdip dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.381 1.778 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 22.352 23.622 0.880 0.930 d1 20.320 20.320 reference 0.800 0.800 reference e 7.620 8.382 0.300 0.330 e1 5.588 7.874 0.220 0.310 e1 2.540 2.540 reference 0.100 0.100 reference ea 7.366 8.128 typical 0.290 0.320 typical eb 7.620 10.160 0.300 0.400 l 3.175 3.810 0.125 0.150 n 1818 1818 s 0.508 1.397 0.020 0.055 s1 0.381 1.270 0.015 0.050 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a l a c e a e b e1 a2
1997 microchip technology inc. ds30234d-page 297 pic16c6x 25.7 28-lead ceramic cerdip dual in-line with windo w (300 mil)) (jw) package group: ceramic cerdip dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.30 5.84 .130 0.230 a1 0.38 0.015 a2 2.92 4.95 0.115 0.195 b 0.35 0.58 0.014 0.023 b1 1.14 1.78 typical 0.045 0.070 typical c 0.20 0.38 typical 0.008 0.015 typical d 34.54 37.72 1.360 1.485 d2 32.97 33.07 reference 1.298 1.302 reference e 7.62 8.25 0.300 0.325 e1 6.10 7.87 0.240 0.310 e 2.54 2.54 typical 0.100 0.100 typical ea 7.62 7.62 reference 0.300 0.300 reference eb 11.43 0.450 l 2.92 5.08 0.115 0.200 n 2828 2828 d1 0.13 0.005 n pin no. 1 indicator area e1 e d b1 b d2 base plane seating plane d1 a1 a2 a l e1 a c e a e b
pic16c6x ds30234d-page 298 1997 microchip technology inc. 25.8 40-lead ceramic cerdip dual in-line with windo w (600 mil) (jw) package group: ceramic cerdip dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.318 5.715 0.170 0.225 a1 0.381 1.778 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.435 52.705 2.025 2.075 d1 48.260 48.260 reference 1.900 1.900 reference e 15.240 15.875 0.600 0.625 e1 12.954 15.240 0.510 0.600 e1 2.540 2.540 reference 0.100 0.100 reference ea 14.986 16.002 typical 0.590 0.630 typical eb 15.240 18.034 0.600 0.710 l 3.175 3.810 0.125 0.150 n 4040 4040 s 1.016 2.286 0.040 0.090 s1 0.381 1.778 0.015 0.070 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a a2 l e1 a c e a e b
1997 microchip technology inc. ds30234d-page 299 pic16c6x 25.9 28-lead ceramic side braz ed dual in-line with windo w (300 mil) (jw) package group: ceramic side brazed dual in-line (cer) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.937 5.030 0.155 0.198 a1 1.016 1.524 0.040 0.060 a2 2.921 3.506 0.115 0.138 a3 1.930 2.388 0.076 0.094 b 0.406 0.508 0.016 0.020 b1 1.219 1.321 typical 0.048 0.052 c 0.228 0.305 typical 0.009 0.012 d 35.204 35.916 1.386 1.414 d1 32.893 33.147 reference 1.295 1.305 e 7.620 8.128 0.300 0.320 e1 7.366 7.620 0.290 0.300 e1 2.413 2.667 typical 0.095 0.105 ea 7.366 7.874 reference 0.290 0.310 eb 7.594 8.179 0.299 0.322 l 3.302 4.064 0.130 0.160 n 2828 2828 s 1.143 1.397 0.045 0.055 s1 0.533 0.737 0.021 0.029 e1 e s base plane seating plane b1 b s1 d l a1 a2 a3 a e1 pin #1 indicator area d1 c ea eb a n
pic16c6x ds30234d-page 300 1997 microchip technology inc. 25.10 28-lead plastic surface mount (ssop - 209 mil bod y 5.30 mm) (ss) package group: plastic ssop symbol millimeters inches min max notes min max notes a 0 8 0 8 a 1.730 1.990 0.068 0.078 a1 0.050 0.210 0.002 0.008 b 0.250 0.380 0.010 0.015 c 0.130 0.220 0.005 0.009 d 10.070 10.330 0.396 0.407 e 5.200 5.380 0.205 0.212 e 0.650 0.650 reference 0.026 0.026 reference h 7.650 7.900 0.301 0.311 l 0.550 0.950 0.022 0.037 n 2828 2828 cp - 0.102 - 0.004 index area n h 123 e e b cp d a a1 base plane seating plane l c a
1997 microchip technology inc. ds30234d-page 301 pic16c6x 25.11 44-lead plastic leaded chip carrier (square) (plcc) package group: plastic leaded chip carrier (plcc) symbol millimeters inches min max notes min max notes a 4.191 4.572 0.165 0.180 a1 2.413 2.921 0.095 0.115 d 17.399 17.653 0.685 0.695 d1 16.510 16.663 0.650 0.656 d2 15.494 16.002 0.610 0.630 d3 12.700 12.700 reference 0.500 0.500 reference e 17.399 17.653 0.685 0.695 e1 16.510 16.663 0.650 0.656 e2 15.494 16.002 0.610 0.630 e3 12.700 12.700 reference 0.500 0.500 reference n 4444 4444 cp 0.102 0.004 lt 0.203 0.381 0.008 0.015 s 0.177 .007 b d-e -a- 0.254 d 1 d 3 3 3 -c- -f- -d- 4 9 8 -b- -e- s 0.177 .007 a f-g s s e e 1 -h- -g- 6 2 3 .010 max 1.524 .060 10 2 11 0.508 .020 1.651 .065 r 1.14/0.64 .045/.025 r 1.14/0.64 .045/.025 1.651 .065 0.508 .020 -h- 11 0.254 .010 max 6 min 0.812/0.661 .032/.026 3 -c- 0.64 .025 min 5 0.533/0.331 .021/.013 0.177 .007 m a f-g s , d-e s 1.27 .050 2 sides a s 0.177 .007 b a s d 3 /e 3 d 2 0.101 .004 0.812/0.661 .032/.026 s 0.38 .015 f-g 4 s 0.38 .015 f-g e 2 d -h- a 1 seating plane 2 sides n pics
pic16c6x ds30234d-page 302 1997 microchip technology inc. 25.12 44-lead plastic surface mount (mqfp 10x10 mm bod y 1.6/0.15 mm lead form) (pq) package group: plastic mqfp symbol millimeters inches min max notes min max notes a 0 7 0 7 a 2.000 2.350 0.078 0.093 a1 0.050 0.250 0.002 0.010 a2 1.950 2.100 0.768 0.083 b 0.300 0.450 typical 0.011 0.018 typical c 0.150 0.180 0.006 0.007 d 12.950 13.450 0.510 0.530 d1 9.900 10.100 0.390 0.398 d3 8.000 8.000 reference 0.315 0.315 reference e 12.950 13.450 0.510 0.530 e1 9.900 10.100 0.390 0.398 e3 8.000 8.000 reference 0.315 0.315 reference e 0.800 0.800 0.031 0.032 l 0.730 1.030 0.028 0.041 n 4444 4444 cp 0.102 0.004 index area 9 b typ 4x base plane a 2 e b a a 1 seating plane 6 d d 1 d 3 4 5 7 e 3 e 1 e 10 0.20 m a-b 0.05 mm/mm d hs s d 0.20 m a-b cs s d 7 5 4 0.20 m a-b cs s d 0.20 m a-b hs s d 0.05 mm/mm a-b c l 1.60 ref. 0.13/0.30 r 0.13 r min. 0.20 min. parting line a
1997 microchip technology inc. ds30234d-page 303 pic16c6x 25.13 44-lead plastic surface mount (tqfp 10x10 mm bod y 1.0/0.10 mm lead form) (tq) note 1: dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.25m/m (0.010? per side. d1 and e1 dimensions including mold mismatch. 2: dimension ? does not include dambar protrusion, allowable dambar protrusion shall be 0.08m/m (0.003?max. 3: this outline conforms to jedec ms-026. package group: plastic tqfp symbol millimeters inches min max notes min max notes a 1.00 1.20 0.039 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 d 11.75 12.25 0.463 0.482 d1 9.90 10.10 0.390 0.398 e 11.75 12.25 0.463 0.482 e1 9.90 10.10 0.390 0.398 l 0.45 0.75 0.018 0.030 e 0.80 bsc 0.031 bsc b 0.30 0.45 0.012 0.018 b1 0.30 0.40 0.012 0.016 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 n 4444 4444 q 0 7 0 7 d e d1 e1 pin#1 2 e 1.0?(0.039? ref. option 1 (top side) pin#1 2 option 2 (top side) 3.0?(0.118? ref. detail a detail b l 1.00 ref. a2 a1 a b b1 c c1 base metal detail a lead finish detail b 11 /13 (4x) 0 min 11 /13 (4x) q r1 0.08 min r 0.08/0.20 gage plane 0.250 l l1 s 0.20 min 1.00 ref detail b
pic16c6x ds30234d-page 304 1997 microchip technology inc. 25.14 p ac ka g e marking inf ormation legend: mm...m xx...x aa bb c d 1 d 2 e microchip part number information customer speci? information* year code (last 2 digits of calender year) week code (week of january 1 is week '01? facility code of the plant at which wafer is manufactured. c = chandler, arizona, u.s.a. mask revision number for microcontroller mask revision number for eeprom assembly code of the plant or country of origin in which part was assembled. in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. note: standard otp marking consists of microchip part number, year code, week code, facility code, mask revision number, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. * mmmmmmmmmmmmm xxxxxxxxxxxxxxxx aabbcde 18-lead pdip 18-lead soic xxxxxxxxxxxx aabbcde xxxxxxxxxxxx mmmmmmmmmm mmmmmm xxxxxxxx aabbcde 18-lead cerdip windowed pic16c61-04/p 9450cba example example -20/so 9449cba pic16c61 pic16c61 /jw 9440cbt example s = tempe, arizona, u.s.a. xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx aabbcae 28-lead pdip (.300 mil) pic16c63-04i/sp 9452can example
1997 microchip technology inc. ds30234d-page 305 pic16c6x p ac ka g e marking inf ormation (cont d) legend: mm...m xx...x aa bb c d 1 e microchip part number information customer speci? information* year code (last 2 digits of calender year) week code (week of january 1 is week '01? facility code of the plant at which wafer is manufactured. c = chandler, arizona, u.s.a. mask revision number for microcontroller assembly code of the plant or country of origin in which part was assembled. in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. note: standard otp marking consists of microchip part number, year code, week code, facility code, mask revision number, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. * s = tempe, arizona, u.s.a. aabbcae xxxxxxxxxxxx xxxxxxxxxxxx aabbcae xxxxxxxxxxxxxxxxxxxx mmmmmmmmmmmmmmmmmmxx 28-lead soic 28-lead ssop 9517sbp 20i/ss025 pic16c62 9515sba pic16c62-20/s0111 example example example 28-lead side brazed skinny windowed xxxxxxxxxxx xxxxxxxxxxx aabbcde example pic16c62/jw 9517sbt 28-lead cerdip skinny windowed xxxxxxxxxxxxxx xxxxxxxxxxxxxx aabbcde pic16c66/jw 9517cat xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx aabbcde 40-lead pdip mmmmmmmmmmmmmm 9510caa example pic16c65-04/p
pic16c6x ds30234d-page 306 1997 microchip technology inc. p ac ka g e marking inf ormation (cont d) legend: mm...m xx...x aa bb c d 1 e microchip part number information customer speci? information* year code (last 2 digits of calender year) week code (week of january 1 is week '01? facility code of the plant at which wafer is manufactured. c = chandler, arizona, u.s.a. mask revision number for microcontroller assembly code of the plant or country of origin in which part was assembled. in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. note: standard otp marking consists of microchip part number, year code, week code, facility code, mask revision number, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. * 44-lead mqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx 44-lead plcc mmmmmmmm aabbcde xxxxxxxxxx xxxxxxxxxx mmmmmmmmm xxxxxxxxxxx aabbcde 40-lead cerdip windowed xxxxxxxxxxx example -04/pq 9444cap pic16c64 example pic16c64 9442can -20/l pic16c67/jw 9450cat example s = tempe, arizona, u.s.a. 44-lead tqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx example -10/tq aabbcde pic16c64a
1997 microchip technology inc. ds30234d-page 307 pic16c6x appendix a: modifications the following are the list of modi?ations over the pic16c5x microcontroller family: 1. instruction word length is increased to 14-bits. this allows larger page sizes both in program memory (2k now as opposed to 512 before) and register ?e (128 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. pa2, pa1, pa0 bits are removed from status register. 3. data memory paging is rede?ed slightly. sta- tus register is modi?d. 4. four new instructions have been added: return, retfie, addlw , and sublw . two instructions tris and option are being phased out although they are kept for compati- bility with pic16c5x. 5. option and tris registers are made address- able. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. reg- isters are reset differently. 10. wake-up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt), are included for more reliable power-up. these tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change feature. 13. timer0 pin is also a port pin (ra4/t0cki) now. 14. fsr is made a full 8-bit register. 15. ?n-circuit programming is made possible. the user can program pic16cxx devices using only ?e pins: v dd , v ss , v pp , rb6 (clock) and rb7 (data in/out). 16. power control register (pcon) is added with a power-on reset status bit (por ).(not on the pic16c61). 17. brown-out reset has been added to the follow- ing devices: pic16c62a/r62/63/r63/64a/r64/65a/r65/66/ 67. appendix b: compatibility to convert code written for pic16c5x to pic16cxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call, goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. rede?e data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h.
pic16c6x ds30234d-page 308 1997 microchip technology inc. appendix c: what? new added pic16cr63 and pic16cr65 devices. added pic16c66 and pic16c67 devices. the pic16c66/67 devices have 368 bytes of data memory distributed in 4 banks and 8k of program memory in 4 pages. these two devices have an enhanced spi that supports both clock phase and polarity. the usart has been enhanced. when upgrading to the pic16c66/67 please note that the upper 16 bytes of data memory in banks 1,2, and 3 are mapped into bank 0. this may require relocation of data memory usage in the user application code. q-cycles for instruction execution were added to sec- tion 14.0 instruction set summary. appendix d: whats changed minor changes, spelling and grammatical changes. divided spi section into spi for the pic16c66/67 (section 11.3) and spi for all other devices (section 11.2). added the following note for the usart. this applies to all devices except the pic16c66 and pic16c67. for the pic16c63/r63/65/65a/r65 the asynchronous high speed mode (brgh = 1) may experience a high rate of receive errors. it is recommended that brgh = 0. if you desire a higher baud rate than brgh = 0 can support, refer to the device errata for additional infor- mation or use the pic16c66/67.
1997 microchip technology inc. ds30234d-page 309 pic16c6x appendix e: pic16/17 microcontrollers e.1 pic12cxxx f amil y of de vices e.2 pic14c000 f amil y of de vices pic12c508 pic12c509 pic12c671 pic12c672 clock maximum frequency of operation (mhz) 4444 memory eprom program memory 512 x 12 1024 x 12 1024 x 14 2048 x 14 data memory (bytes) 25 41 128 128 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 a/d converter (8-bit) channels 4 4 features wake-up from sleep on pin change yes yes yes yes i/o pins 5555 input pins 1111 internal pull-ups yes yes yes yes voltage range (volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 in-circuit serial programming yes yes yes yes number of instructions 33 33 35 35 packages 8-pin dip, soic 8-pin dip, soic 8-pin dip, soic 8-pin dip, soic all pic12c5xx devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic12c5xx devices use serial programming with data pin gp1 and clock pin gp0. pic14c000 clock maximum frequency of operation (mhz) 20 memory eprom program memory (x14 words) 4k data memory (bytes) 192 timer module(s) tmr0 adtmr peripherals serial port(s) (spi/i 2 c, usart) i 2 c with smbus support features slope a/d converter channels 8 external; 6 internal interrupt sources 11 i/o pins 22 voltage range (volts) 2.7-6.0 in-circuit serial programming yes additional on-chip features internal 4mhz oscillator, bandgap reference,temperature sensor, calibration factors, low voltage detector, sleep, hibernate, comparators with programmable references (2) packages 28-pin dip (.300 mil), soic, ssop
pic16c6x ds30234d-page 310 1997 microchip technology inc. e.3 pic16c15x f amil y of de vices e.4 pic16c5x f amil y of de vices pic16c154 pic16cr154 pic16c156 pic16cr156 pic16c158 pic16cr158 clock maximum frequency of operation (mhz) 20 20 20 20 20 20 memory eprom program memory (x12 words) 512 1k 2k rom program memory (x12 words) 512 1k 2k ram data memory (bytes) 25 25 25 25 73 73 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 features i/o pins 12 12 12 12 12 12 voltage range (volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 number of instructions 33 33 33 33 33 33 packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. pic16c52 pic16c54 pic16c54a pic16cr54a pic16c55 pic16c56 clock maximum frequency of operation (mhz) 4202020 2020 memory eprom program memory (x12 words) 384 512 512 512 1k rom program memory (x12 words) 512 ram data memory (bytes) 25 25 25 25 24 25 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 features i/o pins 12 12 12 12 20 12 voltage range (volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.25 number of instructions 33 33 33 33 33 33 packages 18-pin dip, soic 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin dip, soic, ssop 18-pin dip, soic; 20-pin ssop pic16c57 pic16cr57b pic16c58a pic16cr58a clock maximum frequency of operation (mhz) 20 20 20 20 memory eprom program memory (x12 words) 2k 2k rom program memory (x12 words) ?k 2k ram data memory (bytes) 72 72 73 73 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 features i/o pins 20 20 12 12 voltage range (volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 number of instructions 33 33 33 33 packages 28-pin dip, soic, ssop 28-pin dip, soic, ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer (except pic16c52), selectable code protect and high i/o current capability.
1997 microchip technology inc. ds30234d-page 311 pic16c6x e.5 pic16c55 x f amil y of de vices e.6 pic16c62x and pic16c64x f amil y of de vices pic16c554 pic16c556 (1) pic16c558 clock maximum frequency of operation (mhz) 20 20 20 memory eprom program memory (x14 words) 512 1k 2k data memory (bytes) 80 80 128 peripherals timer module(s) tmr0 tmr0 tmr0 comparators(s) internal reference voltage features interrupt sources 3 3 3 i/o pins 13 13 13 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 brown-out reset packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c5xx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local microchip sales of?e for availability of these devices. pic16c620 pic16c621 pic16c622 pic16c642 pic16c662 clock maximum frequency of operation (mhz) 20 20 20 20 20 memory eprom program memory (x14 words) 512 1k 2k 4k 4k data memory (bytes) 80 80 128 176 176 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 comparators(s) 22222 internal reference voltage yes yes yes yes yes features interrupt sources 44445 i/o pins 13 13 13 22 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 3.0-6.0 3.0-6.0 brown-out reset yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin pdip, soic, windowed cdip 40-pin pdip, windowed cdip; 44-pin plcc, mqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c62x and pic16c64x family devices use serial programming with clock pin rb6 and data pin rb7.
pic16c6x ds30234d-page 312 1997 microchip technology inc. e.7 pic16c7xx f amil y of de v ces pic16c710 pic16c71 pic16c711 pic16c715 pic16c72 pic16cr72 (1) clock maximum frequency of operation (mhz) 20 20 20 20 20 20 memory eprom program memory (x14 words) 512 1k 1k 2k 2k rom program memory (14k words) 2k data memory (bytes) 36 36 68 128 128 128 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/ pwm module(s) 1 1 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c parallel slave port a/d converter (8-bit) channels 4 4 4 4 5 5 features interrupt sources 4 4 4 4 8 8 i/o pins 13 13 13 13 22 22 voltage range (volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5 in-circuit serial programming yes yes yes yes yes yes brown-out reset yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin sdip, soic, ssop 28-pin sdip, soic, ssop pic16c73a pic16c74a pic16c76 pic16c77 clock maximum frequency of oper- ation (mhz) 20 20 20 20 memory eprom program memory (x14 words) 4k 4k 8k 8k data memory (bytes) 192 192 368 368 peripherals timer module(s) tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm mod- ule(s) 2222 serial port(s) (spi/i 2 c, us- art) spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart parallel slave port yes yes a/d converter (8-bit) channels 5858 features interrupt sources 11 12 11 12 i/o pins 22 33 22 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 in-circuit serial programming yes yes yes yes brown-out reset yes yes yes yes packages 28-pin sdip, soic 40-pin dip; 44-pin plcc, mqfp, tqfp 28-pin sdip, soic 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capabi l- ity. all pic16c7xx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local microchip sales of?e for availability of these devices.
1997 microchip technology inc. ds30234d-page 313 pic16c6x e.8 pic16c 8x f amil y of de vices e.9 pic16c9xx f amil y of de vices pic16f83 pic16cr83 pic16f84 pic16cr84 clock maximum frequency of operation (mhz) 10 10 10 10 flash program memory 512 1k memory eeprom program memory rom program memory 512 1k data memory (bytes) 36 36 68 68 data eeprom (bytes) 64 64 64 64 peripher- als timer module(s) tmr0 tmr0 tmr0 tmr0 features interrupt sources 4 4 4 4 i/o pins 13 13 13 13 voltage range (volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0 packages 18-pin dip, soic 18-pin dip, soic 18-pin dip, soic 18-pin dip, soic all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capabi l- ity. all pic16c8x family devices use serial programming with clock pin rb6 and data pin rb7. pic16c923 pic16c924 clock maximum frequency of operation (mhz) 8 8 memory eprom program memory 4k 4k data memory (bytes) 176 176 peripherals timer module(s) tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm module(s) 1 1 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c parallel slave port a/d converter (8-bit) channels 5 lcd module 4 com, 32 seg 4 com, 32 seg features interrupt sources 8 9 i/o pins 25 25 input pins 27 27 voltage range (volts) 3.0-6.0 3.0-6.0 in-circuit serial programming yes yes brown-out reset packages 64-pin sdip (1) , tqfp; 68-pin plcc, die 64-pin sdip (1) , tqfp; 68-pin plcc, die all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capa- bility. all pic16c9xx family devices use serial programming with clock pin rb6 and data pin rb7.
pic16c6x ds30234d-page 314 1997 microchip technology inc. e.10 pic17cxxx f ami l y of de vices pic17c42a pic17cr42 pic17c43 pic17cr43 pic17c44 clock maximum frequency of operation (mhz) 33 33 33 33 33 memory eprom program memory (words) 2k 4k 8k rom program memory (words) 2k 4k ram data memory (bytes) 232 232 454 454 454 peripherals timer module(s) tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 captures/pwm module(s) 22222 serial port(s) (usart) yes yes yes yes yes features hardware multiply yes yes yes yes yes external interrupts yes yes yes yes yes interrupt sources 11 11 11 11 11 i/o pins 33 33 33 33 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 number of instructions 58 58 58 58 58 packages 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp pic17c752 pic17c756 clock maximum frequency of operation (mhz) 33 33 memory eprom program memory (words) 8k 16k rom program memory (words) ram data memory (bytes) 454 902 peripherals timer module(s) tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 captures/pwm module(s) 4/3 4/3 serial port(s) (usart) 2 2 features hardware multiply yes yes external interrupts yes yes interrupt sources 18 18 i/o pins 50 50 voltage range (volts) 3.0-6.0 3.0-6.0 number of instructions 58 58 packages 64-pin dip; 68-pin lcc, 68-pin tqfp 64-pin dip; 68-pin lcc, 68-pin tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability.
1997 microchip technology inc. ds30234d-page 315 pic16c6x pin compatibility devices that have the same package type and v dd , v ss and mclr pin locations are said to be pin compatible. this allows these different devices to operate in the same socket. compatible devices may only requires minor software modi?ation to allow proper operation in the application socket (ex., pic16c56 and pic16c61 devices). not all devices in the same package size are pin compatible; for example, the pic16c62 is compatible with the pic16c63, but not the pic16c55. pin compatibility does not mean that the devices offer the same features. as an example, the pic16c54 is pin compatible with the pic16c71, but does not have an a/d converter, weak pull-ups on portb, or interrupts. table e-1: pin compatible devices pin compatible devices package pic12c508, pic12c509, pic12c671, pic12c672 8-pin pic16c154, pic16cr154, pic16c156, pic16cr156, pic16c158, pic16cr158, pic16c52, pic16c54, pic16c54a, pic16cr54a, pic16c56, pic16c58a, pic16cr58a, pic16c61, pic16c554, pic16c556, pic16c558 pic16c620, pic16c621, pic16c622 pic16c641, pic16c642, pic16c661, pic16c662 pic16c710, pic16c71, pic16c711, pic16c715 pic16f83, pic16cr83, pic16f84a, pic16cr84 18-pin, 20-pin pic16c55, pic16c57, pic16cr57b 28-pin pic16cr62, pic16c62a, pic16c63, pic16cr63, pic16c66, pic16c72, pic16c73a, pic16c76 28-pin pic16cr64, pic16c64a, pic16c65a, pic16cr65, pic16c67, pic16c74a, pic16c77 40-pin pic17cr42, pic17c42a, pic17c43, pic17cr43, pic17c44 40-pin pic16c923, pic16c924 64/68-pin pic17c756, pic17c752 64/68-pin
pic16c6x ds30234d-page 316 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30234d-page 317 pic16c6x index numerics 9-bit receive enable bit, rx9 ........................................... 106 9-bit transmit enable bit, tx9 .......................................... 105 9th bit of received data, rx9d .......................................... 106 9th bit of transmit data, tx9d ........................................... 105 a absolute maximum ratings.............................. 163, 183, 199, 215, 231, 247, 263 ack ..................................................................... 96, 100, 101 alu ....................................................................................... 9 application notes an552 (implementing wake-up on key stroke) ......... 53 an556 (implementing a table read) ......................... 48 an594 (using the ccp modules) ............................... 77 architectural overview .......................................................... 9 b baud rate formula........................................................... 107 baud rate generator........................................................ 107 baud rates asynchronous mode ................................................. 108 error, calculating ...................................................... 107 rx pin sampling, timing diagrams.................. 110, 111 sampling ................................................................... 110 synchronous mode ................................................... 108 bf ......................................................................... 84, 89, 100 block diagrams capture mode operation ............................................ 78 compare mode ........................................................... 79 crystal oscillator, ceramic resonator...................... 125 external brown-out protection .................................. 135 external parallel resonant crystal circuit ................ 127 external power-on reset .......................................... 135 external series resonant crystal circuit.................. 127 i 2 c mode..................................................................... 99 in-circuit programming connections......................... 142 interrupt logic ........................................................... 137 on-chip reset circuit................................................ 128 parallel slave port, portd-porte .......................... 61 pic16c61 ................................................................... 10 pic16c62 ................................................................... 11 pic16c62a ................................................................. 11 pic16c63 ................................................................... 12 pic16c64 ................................................................... 11 pic16c64a ................................................................. 11 pic16c65 ................................................................... 12 pic16c65a ................................................................. 12 pic16c66 ................................................................... 13 pic16c67 ................................................................... 13 pic16cr62................................................................. 11 pic16cr63................................................................. 12 pic16cr64................................................................. 11 pic16cr65................................................................. 12 portc ....................................................................... 55 portd (i/o mode) ..................................................... 57 porte (i/o mode) ..................................................... 58 pwm ........................................................................... 80 ra3:ra0 pins ............................................................. 51 ra4/t0cki pin ............................................................ 51 ra5 pin ....................................................................... 51 rb3:rb0 pins ............................................................. 54 rb7:rb4 pins ....................................................... 53, 54 rc oscillator mode................................................... 127 spi master/slave connection......................................87 ssp in i 2 c mode .........................................................99 ssp in spi mode...................................................86, 91 timer0 .........................................................................65 timer0/wdt prescaler ................................................68 timer1 .........................................................................72 timer2 .........................................................................75 usart receive ........................................................114 usart transmit .......................................................112 watchdog timer ........................................................140 bor...................................................................................129 bor .............................................................................47, 131 brgh ................................................................................105 brown-out reset (bor).....................................................129 brown-out reset status bit, bor ........................................47 buffer full status bit, bf................................................84, 89 c c ..........................................................................................35 c compiler.........................................................................161 capture block diagram .............................................................78 mode............................................................................78 pin configuration .........................................................78 prescaler .....................................................................79 software interrupt ........................................................78 capture interrupt .................................................................78 capture/compare/pwm (ccp) capture mode..............................................................78 capture mode block diagram .....................................78 ccp1 ...........................................................................77 ccp2 ...........................................................................77 compare mode............................................................79 compare mode block diagram ...................................79 overview......................................................................63 prescaler .....................................................................79 pwm block diagram ...................................................80 pwm mode..................................................................80 pwm, example frequencies/resolutions ...................81 section.........................................................................77 carry......................................................................................9 carry bit ...............................................................................35 ccp module interaction ......................................................77 ccp pin configuration.........................................................78 ccp to timer resource use ...............................................77 ccp1 interrupt enable bit, ccp1ie.....................................38 ccp1 interrupt flag bit, ccp1if .........................................41 ccp1 mode select bits .......................................................78 ccp1con .............................................24, 26, 28, 30, 32, 34 ccp1ie................................................................................38 ccp1if................................................................................41 ccp1m3:ccm1m0..............................................................78 ccp1x:ccp1y....................................................................78 ccp2 interrupt enable bit, ccp2ie.....................................45 ccp2 interrupt flag bit, ccp2if .........................................46 ccp2 mode select bits .......................................................78 ccp2con .............................................24, 26, 28, 30, 32, 34 ccp2ie................................................................................45 ccp2if................................................................................46 ccp2m3:ccp2m0 ..............................................................78 ccp2x:ccp2y....................................................................78 ccpr1h................................................24, 26, 28, 30, 32, 34 ccpr1l ................................................24, 26, 28, 30, 32, 34 ccpr2h................................................24, 26, 28, 30, 32, 34 ccpr2l ................................................24, 26, 28, 30, 32, 34 cke .....................................................................................89 ckp ...............................................................................85, 90
pic16c6x ds30234d-page 318 1997 microchip technology inc. clearing interrupts............................................................... 53 clock polarity select bit, ckp ....................................... 85, 90 clock polarity, spi mode .................................................... 87 clock source select bit, csrc......................................... 105 clocking scheme ................................................................ 18 code examples changing between capture prescalers...................... 79 ensuring interrupts are globally disabled ................ 136 indirect addressing ..................................................... 49 initializing porta....................................................... 51 initializing portb....................................................... 53 initializing portc....................................................... 55 loading the sspbuf register ................................... 86 loading the sspbuf register..................................... 91 reading a 16-bit free-running timer.......................... 73 read-modify-write on an i/o port............................... 60 saving status, w, and pclath registers ............... 139 subroutine call, page0 to page1................................ 49 code protection ................................................................ 142 compare block diagram............................................................. 79 mode ........................................................................... 79 pin configuration ........................................................ 79 software interrupt ....................................................... 79 special event trigger.................................................. 79 computed goto ................................................................ 48 configuration bits.............................................................. 123 configuration word, diagram............................................ 124 connecting two microcontrollers........................................ 87 continuous receive enable bit, cren............................. 106 cren ................................................................................ 106 csrc ................................................................................ 105 d d/a ................................................................................ 84, 89 data/address bit, d/a .................................................... 84, 89 data memory organization................................................................ 20 section ........................................................................ 20 data sheet compatibility ............................................................. 307 modifications ............................................................. 307 what? new............................................................... 308 dc ....................................................................................... 35 dc characteristics .. 164, 184, 200, 216, 232, 248, 264 development support ....................................................... 159 development tools ........................................................... 159 device drawings 18-lead ceramic cerdip dual in-line with window (300 mil) ............................................... 296 18-lead plastic dual in-line (300 mil) ....................... 291 18-lead plastic surface mount (soic - wide, 300 mil body).................................... 294 28-lead ceramic cerdip dual in-line with window (300 mil)) ..................................................... 297 28-lead ceramic side brazed dual in-line with window (300 mil) ............................................... 299 28-lead plastic dual in-line (300 mil) ....................... 292 28-lead plastic surface mount (soic - wide, 300 mil body)..................................... 295 28-lead plastic surface mount (ssop - 209 mil body 5.30 mm)............................... 300 40-lead ceramic cerdip dual in-line with window (600 mil) ............................................... 298 40-lead plastic dual in-line (600 mil) ....................... 293 44-lead plastic leaded chip carrier (square)......... 301 44-lead plastic surface mount (mqfp 10x10 mm body 1.6/0.15 mm lead form) ....... 302, 303 device varieties.................................................................... 7 digit carry............................................................................. 9 digit carry bit ...................................................................... 35 direct addressing ............................................................... 49 e electrical characteristics .. 163, 183, 199, 215, 231, 247, 263 external clock synchronization, tmr0 .............................. 67 f family of devices pic12cxxx.............................................................. 309 pic14c000 ............................................................... 309 pic16c15x............................................................... 310 pic16c55x............................................................... 311 pic16c5x................................................................. 310 pic16c62x and pic16c64x.................................... 311 pic16c6x..................................................................... 6 pic16c7xx .............................................................. 312 pic16c8x................................................................. 313 pic16c9xx .............................................................. 313 pic17cxx ................................................................ 314 ferr ................................................................................ 106 framing error bit, ferr ................................................... 106 fsr......................... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 fuzzy logic dev. system ( fuzzy tech -mp)........... 159, 161 g general description .............................................................. 5 general purpose registers ................................................ 20 gie...................................................................................... 37 global interrupt enable bit, gie.......................................... 37 graphs pic16c6x................................................................. 281 pic16c61 ................................................................. 173 h high baud rate select bit, brgh .................................... 105 i i/o ports, section................................................................ 51 i 2 c addressing................................................................ 100 addressing i 2 c devices.............................................. 96 arbitration ................................................................... 98 block diagram ............................................................ 99 clock synchronization ................................................ 98 combined format....................................................... 97 i 2 c operation.............................................................. 99 i 2 c overview .............................................................. 95 initiating and terminating data transfer .................... 95 master mode............................................................. 103 master-receiver sequence ........................................ 97 master-transmitter sequence .................................... 97 mode........................................................................... 99 mode selection........................................................... 99 multi-master................................................................ 98 multi-master mode.................................................... 103 reception ................................................................. 101 reception timing diagram ....................................... 101 scl and sda pins.................................................... 100 slave mode............................................................... 100 start........................................................................ 95 stop.................................................................... 95, 96
1997 microchip technology inc. ds30234d-page 319 pic16c6x transfer acknowledge ................................................ 96 transmission............................................................. 102 id locations ...................................................................... 142 idle_mode ..................................................................... 104 in-circuit serial programming............................................ 142 indf...................................................... 24, 26, 28, 30, 32, 34 indirect addressing ............................................................. 49 instruction cycle ................................................................. 18 instruction flow/pipelining .................................................. 18 instruction format ............................................................. 143 instruction set addlw ..................................................................... 145 addwf..................................................................... 145 andlw ..................................................................... 145 andwf..................................................................... 145 bcf........................................................................... 146 bsf ........................................................................... 146 btfsc ...................................................................... 146 btfss ...................................................................... 147 call ......................................................................... 147 clrf......................................................................... 148 clrw ....................................................................... 148 clrwdt................................................................... 148 comf ....................................................................... 149 decf ........................................................................ 149 decfsz.................................................................... 149 goto ....................................................................... 150 incf.......................................................................... 150 incfsz ..................................................................... 151 iorlw ...................................................................... 151 iorwf ...................................................................... 152 movf........................................................................ 152 movlw .................................................................... 152 movwf .................................................................... 152 nop .......................................................................... 153 option .................................................................... 153 retfie ..................................................................... 153 retlw ..................................................................... 154 return ................................................................... 154 rlf ........................................................................... 155 rrf........................................................................... 155 sleep ...................................................................... 156 sublw ..................................................................... 156 subwf ..................................................................... 157 swapf ..................................................................... 157 tris.......................................................................... 157 xorlw..................................................................... 158 xorwf..................................................................... 158 section ...................................................................... 143 summary table......................................................... 144 intcon .................. 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 inte.................................................................................... 37 intedg .............................................................................. 36 interrupt edge select bit, intedg...................................... 36 interrupt on change feature............................................... 53 interrupts section ...................................................................... 136 ccp ............................................................................ 78 ccp1 .......................................................................... 38 ccp1 flag bit.............................................................. 41 ccp2 enable bit ......................................................... 45 ccp2 flag bit.............................................................. 46 context saving.......................................................... 139 parallel slave port flag bit.......................................... 43 parallel slave prot read/write enable bit .................. 39 port rb ....................................................................... 53 rb0/int .............................................................. 54, 138 rb0/int timing diagram ..........................................138 receive flag bit...........................................................42 timer0 .........................................................................65 timer0, timing.............................................................66 timing diagram, wake-up from sleep ....................142 tmr0.........................................................................138 usart receive enable bit .........................................39 usart transmit enable bit ........................................39 usart transmit flag bit.............................................42 wake-up ....................................................................141 wake-up from sleep ...............................................141 intf.....................................................................................37 irp.......................................................................................35 l loading the program counter .............................................48 m mpasm assembler ...................................................159, 160 mplab-c...........................................................................161 mpsim software simulator .......................................159, 161 o oerr ................................................................................106 one-time-programmable devices ........................................7 opcode ...........................................................................143 open-drain ..........................................................................51 option.................................................25, 27, 29, 31, 33, 34 oscillator start-up timer (ost) .................................123, 129 oscillators block diagram, external parallel resonant crystal ..127 capacitor selection .....................................................73 configuration .............................................................125 external crystal circuit ..............................................127 hs......................................................................125, 130 lp ......................................................................125, 130 rc, block diagram ....................................................127 rc, section ...............................................................127 xt ..............................................................................125 overrun error bit, oerr ...................................................106 p p ....................................................................................84, 89 packaging information.......................................................291 parallel slave port portd ........................................................................57 section.........................................................................61 parallel slave port interrupt flag bit, pspif .......................43 parallel slave port read/write interrupt enable bit, pspie 39 pcl..........................24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 pclath ............24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 48 pcon ............................................25, 27, 29, 31, 33, 34, 130 pd ................................................................................35, 131 peie ....................................................................................37 peripheral interrupt enable bit, peie...................................37 picdem-1 low-cost pic16/17 demo board ............159, 160 picdem-2 low-cost pic16cxx demo board..........159, 160 picdem-3 low-cost pic16c9xxx demo board .............160 picmaster in-circuit emulator.......................................159 picstart low-cost development system .....................159 pie1.......................................................25, 27, 29, 31, 33, 34 pie2.......................................................25, 27, 29, 31, 33, 34 pin compatible devices ....................................................315 pin functions mclr /v pp ...................................................................16
pic16c6x ds30234d-page 320 1997 microchip technology inc. osc1/clkin............................................................... 16 osc2/clkout........................................................... 16 porta........................................................................ 52 portb........................................................................ 54 portc ....................................................................... 55 portd ....................................................................... 57 porte........................................................................ 59 ra4/t0cki............................................................ 16, 52 ra5/ss ................................................................. 16, 52 rb0/int ................................................................ 16, 54 rb6 ........................................................................... 142 rb7 ........................................................................... 142 rc0/t1osi/t1cki ...................................................... 55 rc0/t1oso/t1cki .............................................. 16, 55 rc1/t1osi ................................................................. 55 rc1/t1osi/ccp2................................................. 16, 55 rc1/t1oso................................................................ 55 rc2/ccp1 ...................................................... 16, 55, 56 rc3/sck/scl ................................................ 16, 55, 56 rc4/sdi/sda ................................................. 16, 55, 56 rc5/sdo ........................................................ 16, 55, 56 rc6/tx/ck ..................................... 16, 55, 56, 105?20 rc7/rx/dt ..................................... 16, 55, 56, 105?20 rd7/psp7:rd0/psp0 .......................................... 17, 57 re0/rd ........................................................... 17, 59, 61 re1/wr .......................................................... 17, 59, 61 re2/cs ........................................................... 17, 59, 61 sck....................................................................... 86?8 sdi ........................................................................ 86?8 sdo ...................................................................... 86?8 ss ......................................................................... 86?8 v dd ............................................................................. 17 v ss .............................................................................. 17 pir1 ...................................................... 24, 26, 28, 30, 32, 34 pir2 ...................................................... 24, 26, 28, 30, 32, 34 pop..................................................................................... 48 por ............................................................................ 47, 131 por time-out sequence on power-up ........................... 134 port rb interrupt ................................................................. 53 porta............................................ 24, 26, 28, 30, 32, 34, 51 portb............................................ 24, 26, 28, 30, 32, 34, 53 portb interrupt on change............................................. 138 portb pull-up enable bit, rbpu ....................................... 36 portc............................................ 24, 26, 28, 30, 32, 34, 55 portd............................................ 24, 26, 28, 30, 32, 34, 57 porte............................................ 24, 26, 28, 30, 32, 34, 58 ports bi-directional ............................................................... 60 i/o programming considerations................................ 60 porta........................................................................ 16 portb........................................................................ 16 portc ....................................................................... 16 portd ....................................................................... 17 porte........................................................................ 17 successive operations on an i/o port........................ 60 power/control status register, pcon ............................. 130 power-down bit ................................................................... 35 power-down mode ............................................................ 141 power-on reset (por) ..................................................... 129 power-on reset status bit, por ......................................... 47 power-up timer (pwrt)........................................... 123, 129 pr2 ....................................................... 25, 27, 29, 31, 33, 34 prescaler ............................................................................. 68 prescaler assignment bit, psa ........................................... 36 prescaler rate select bits, ps2:ps0 .................................. 36 pro mate universal programmer .................................. 159 program memory map....................................................................... 19, 20 organization ............................................................... 19 paging ........................................................................ 48 section........................................................................ 19 programming while in-circuit............................................ 142 ps2:ps0 ............................................................................. 36 psa..................................................................................... 36 pspie ................................................................................. 39 pspif ................................................................................. 43 pull-ups............................................................................... 53 push.................................................................................. 48 pwm block diagram ............................................................ 80 calculations ................................................................ 81 mode........................................................................... 80 output timing ............................................................. 80 pwm least significant bits ................................................. 78 q quadrature clocks.............................................................. 18 quick-turnaround-production .............................................. 7 r r/w bit ............................................ 84, 89, 96, 100, 101, 102 ra0 pin ............................................................................... 51 ra1 pin ............................................................................... 51 ra2 pin ............................................................................... 51 ra3 pin ............................................................................... 51 ra4/t0cki pin.................................................................... 51 ra5 pin ............................................................................... 51 rb port change interrupt enable bit, rbie........................ 37 rb port change interrupt flag bit, rbif ............................ 37 rb0..................................................................................... 54 rb0/int ............................................................................ 138 rb0/int external interrupt enable bit, inte ...................... 37 rb0/int external interrupt flag bit, intf........................... 37 rb1..................................................................................... 54 rb2..................................................................................... 54 rb3..................................................................................... 54 rb4..................................................................................... 53 rb5..................................................................................... 53 rb6..................................................................................... 53 rb7..................................................................................... 53 rbie ................................................................................... 37 rbif.................................................................................... 37 rbpu ............................................................................ 36, 53 rc oscillator..................................................................... 130 rcie ................................................................................... 39 rcif ................................................................................... 42 rcreg................................................. 24, 26, 28, 30, 32, 34 rcsta.......................................... 24, 26, 28, 30, 32, 34, 106 rcv_mode ..................................................................... 104 read only memory............................................................... 7 read/write bit information, r/w ................................... 84, 89 receive and control register........................................... 106 receive overflow detect bit, sspov ................................. 85 receive overflow indicator bit, sspov.............................. 90 register bank select bit, indirect........................................ 35 register bank select bits. direct ........................................ 35
1997 microchip technology inc. ds30234d-page 321 pic16c6x registers ccp1con diagram .............................................................. 78 section................................................................ 78 summary .................................... 24, 26, 28, 30, 32 ccp2con diagram .............................................................. 78 section................................................................ 78 summary ................................................ 26, 30, 32 ccpr1h summary .................................... 24, 26, 28, 30, 32 ccpr1l summary .................................... 24, 26, 28, 30, 32 ccpr2h summary ................................................ 26, 30, 32 ccpr2l summary ................................................ 26, 30, 32 fsr indirect addressing ............................................. 49 summary .............................. 24, 26, 28, 30, 32, 34 indf indirect addressing ............................................. 49 summary .............................. 24, 26, 28, 30, 32, 34 intcon diagram .............................................................. 37 section................................................................ 37 summary .............................. 24, 26, 28, 30, 32, 34 option diagram .............................................................. 36 section................................................................ 36 summary .............................. 25, 27, 29, 31, 33, 34 pcl section................................................................ 48 summary .............................. 24, 26, 28, 30, 32, 34 pclath section................................................................ 48 summary .............................. 24, 26, 28, 30, 32, 34 pcon diagram .............................................................. 47 section................................................................ 47 summary .................................... 25, 27, 29, 31, 33 pie1 diagram .............................................................. 40 section................................................................ 38 summary .................................... 25, 27, 29, 31, 33 pie2 diagram .............................................................. 45 section................................................................ 45 summary ................................................ 27, 31, 33 pir1 diagram .............................................................. 44 section................................................................ 41 summary .................................... 24, 26, 28, 30, 32 pir2 diagram .............................................................. 46 section................................................................ 46 summary ................................................ 26, 30, 32 porta section................................................................ 51 summary .................................... 24, 26, 28, 30, 32 portb section................................................................ 53 summary .............................. 24, 26, 28, 30, 32, 34 portc section................................................................ 55 summary .................................... 24, 26, 28, 30, 32 portd section ................................................................57 summary .................................................28, 30, 32 porte section ................................................................58 summary .................................................28, 30, 32 pr2 summary .....................................25, 27, 29, 31, 33 rcreg summary .................................................26, 30, 32 rcsta diagram.............................................................106 summary .................................................26, 30, 32 spbrg summary .................................................27, 31, 33 sspbuf section ................................................................86 summary .....................................24, 26, 28, 30, 32 sspcon diagram...............................................................85 summary .....................................24, 26, 28, 30, 32 sspsr section ................................................................86 sspstat ....................................................................89 diagram...............................................................84 section ................................................................84 summary .....................................25, 27, 29, 31, 33 status diagram...............................................................35 section ................................................................35 summary ...............................24, 26, 28, 30, 32, 34 t1con diagram...............................................................71 section ................................................................71 summary .....................................24, 26, 28, 30, 32 t2con diagram...............................................................75 section ................................................................75 summary .....................................24, 26, 28, 30, 32 tmr0 summary ...............................24, 26, 28, 30, 32, 34 tmr1h summary .....................................24, 26, 28, 30, 32 tmr1l summary .....................................24, 26, 28, 30, 32 tmr2...........................................................................75 summary .....................................24, 26, 28, 30, 32 trisa section ................................................................51 summary .....................................25, 27, 29, 31, 33 trisb section ................................................................53 summary ...............................25, 27, 29, 31, 33, 34 trisc section ................................................................55 summary .....................................25, 27, 29, 31, 33 trisd section ................................................................57 summary .................................................29, 31, 33 trise diagram...............................................................58 section ................................................................58 summary .................................................29, 31, 33 txreg summary .................................................26, 30, 32
pic16c6x ds30234d-page 322 1997 microchip technology inc. txsta diagram ............................................................ 105 section .............................................................. 105 summary....................................................... 31, 33 w................................................................................... 9 special function registers, initialization conditions ................................................................. 132 special function registers, reset conditions.......... 131 special function register summary... 24, 26, 28, 30, 32 file maps .................................................................... 21 resets ............................................................................... 128 rom...................................................................................... 7 rp0 bit .......................................................................... 20, 35 rp1 ..................................................................................... 35 rx9 ................................................................................... 106 rx9d................................................................................. 106 s s.................................................................................... 84, 89 sci - see universal synchronous asynchronous receiver transmitter (usart) sck..................................................................................... 86 scl ................................................................................... 100 sdi ...................................................................................... 86 sdo .................................................................................... 86 serial port enable bit, spen............................................. 106 serial programming .......................................................... 142 serial programming, block diagram ................................. 142 serialized quick-turnaround-production .............................. 7 single receive enable bit, sren ..................................... 106 slave mode scl ........................................................................... 100 sda........................................................................... 100 sleep mode............................................................. 123, 141 smp .................................................................................... 89 software simulator (mpsim)............................................. 161 spbrg.................................................. 25, 27, 29, 31, 33, 34 special features, section ................................................. 123 spen ................................................................................ 106 spi block diagram....................................................... 86, 91 master mode ............................................................... 92 master mode timing ................................................... 93 mode ........................................................................... 86 serial clock................................................................. 91 serial data in .............................................................. 91 serial data out ........................................................... 91 slave mode timing ..................................................... 94 slave mode timing diagram....................................... 93 slave select ................................................................ 91 spi clock ..................................................................... 92 spi mode .................................................................... 91 sspcon..................................................................... 90 sspstat.................................................................... 89 spi clock edge select bit, cke.......................................... 89 spi data input sample phase select bit, smp................... 89 spi mode ............................................................................ 86 sren ................................................................................ 106 ss ....................................................................................... 86 ssp module overview ........................................................ 83 section ........................................................................ 83 sspbuf...................................................................... 92 sspcon..................................................................... 90 sspsr........................................................................ 92 sspstat.................................................................... 89 ssp in i 2 c mode - see i 2 c sspadd ......................................... 25, 27, 29, 31, 33, 34, 99 sspbuf ......................................... 24, 26, 28, 30, 32, 34, 99 sspcon................................... 24, 26, 28, 30, 32, 34, 85, 90 sspen.......................................................................... 85, 90 sspie ................................................................................. 38 sspif ................................................................................. 41 sspm3:sspm0 ............................................................ 85, 90 sspov ................................................................. 85, 90, 100 sspstat ................................. 25, 27, 29, 31, 33, 34, 84, 99 sspstat register ............................................................. 89 stack................................................................................... 48 start bit, s ..................................................................... 84, 89 status.................. 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 status bits ................................................................. 130, 131 status bits during various resets.................................... 131 stop bit, p ..................................................................... 84, 89 switching prescalers .......................................................... 69 sync,usart mode select bit, sync............................. 105 synchronizing clocks, tmr0.............................................. 67 synchronous serial port (ssp) block diagram, spi mode .......................................... 86 spi master/slave diagram ......................................... 87 spi mode.................................................................... 86 synchronous serial port enable bit, sspen................ 85, 90 synchronous serial port interrupt enable bit, sspie ......... 38 synchronous serial port interrupt flag bit, sspif ............. 41 synchronous serial port mode select bits, sspm3:sspm0 ............................................................ 85, 90 synchronous serial port module ........................................ 83 synchronous serial port status register ........................... 89 t t0cs................................................................................... 36 t0ie .................................................................................... 37 t0if .................................................................................... 37 t0se................................................................................... 36 t1ckps1:t1ckps0........................................................... 71 t1con.................................................. 24, 26, 28, 30, 32, 34 t1oscen........................................................................... 71 t1sync .............................................................................. 71 t2ckps1:t2ckps0........................................................... 75 t2con............................................ 24, 26, 28, 30, 32, 34, 75 time-out ........................................................................... 130 time-out bit......................................................................... 35 time-out sequence .......................................................... 130 timer modules overview, all ............................................................... 63 timer0 block diagram .................................................... 65 counter mode..................................................... 65 external clock .................................................... 67 interrupt .............................................................. 65 overview............................................................. 63 prescaler ............................................................ 68 section................................................................ 65 timer mode ........................................................ 65 timing diagramtiiming diagrams timer0 ................................................................ 65 tmr0 register..................................................... 65 timer1 block diagram .................................................... 72 capacitor selection ............................................ 73 counter mode, asynchronous ............................ 73 counter mode, synchronous.............................. 72 external clock .................................................... 73 oscillator............................................................. 73
1997 microchip technology inc. ds30234d-page 323 pic16c6x overview............................................................. 63 prescaler............................................................. 72 read/write in asynchronous counter mode ...... 73 section................................................................ 71 synchronizing with external clock...................... 72 timer mode......................................................... 72 tmr1 register pair ............................................ 71 timer2 block diagram .................................................... 75 overview............................................................. 63 postscaler ........................................................... 75 prescaler............................................................. 75 timer0 clock synchronization, delay ................................. 67 timer0 interrupt ................................................................ 138 timer1 clock source select bit, tmr1cs .......................... 71 timer1 external clock input synchronization control bit, t1sync ........................................................... 71 timer1 input clock prescale select bits ............................. 71 timer1 mode selection ....................................................... 78 timer1 on bit, tmr1on ..................................................... 71 timer1 oscillator enable control bit, t1oscen ................ 71 timer2 clock prescale select bits, t2ckps1:t2ckps0 ........................................................... 75 timer2 module .................................................................... 75 timer2 on bit, tmr2on ..................................................... 75 timer2 output postscale select bits, toutps3:toutps0.......................................................... 75 timing diagrams brown-out reset ....................................................... 129 i 2 c clock synchronization .......................................... 98 i 2 c data transfer wait state ...................................... 96 i 2 c multi-master arbitration......................................... 98 i 2 c reception (7-bit address) ................................... 101 pic16c61 clkout and i/o .............................................. 170 external clock................................................... 169 oscillator start-up timer ................................... 171 power-up timer ................................................ 171 reset ................................................................ 171 timer0............................................................... 172 watchdog timer ............................................... 171 pic16c62 capture/compare/pwm ................................... 193 clkout and i/o .............................................. 190 external clock................................................... 189 i 2 c bus data..................................................... 197 i 2 c bus start/stop bits ..................................... 196 oscillator start-up timer ................................... 191 power-up timer ................................................ 191 reset ................................................................ 191 spi mode .......................................................... 195 timer0............................................................... 192 timer1............................................................... 192 watchdog timer ............................................... 191 pic16c62a brown-out reset ............................................... 207 capture/compare/pwm ................................... 209 clkout and i/o .............................................. 206 external clock................................................... 205 i 2 c bus data..................................................... 213 i 2 c bus start/stop bits ..................................... 212 oscillator start-up timer ................................... 207 power-up timer ................................................ 207 reset ................................................................ 207 spi mode .......................................................... 211 timer0............................................................... 208 timer1............................................................... 208 watchdog timer ................................................207 pic16c63 brown-out reset................................................239 capture/compare/pwm ....................................241 clkout and i/o ...............................................238 external clock ...................................................237 i 2 c bus data .....................................................245 i 2 c bus start/stop bits ......................................244 oscillator start-up timer ...................................239 power-up timer.................................................239 reset .................................................................239 spi mode...........................................................243 timer0 ...............................................................240 timer1 ...............................................................240 usart synchronous receive (master/slave) ..................................................246 watchdog timer ................................................239 pic16c64 capture/compare/pwm ....................................193 clkout and i/o ...............................................190 external clock ...................................................189 i 2 c bus data .....................................................197 i 2 c bus start/stop bits ......................................196 oscillator start-up timer ...................................191 parallel slave port.............................................194 power-up timer.................................................191 reset .................................................................191 spi mode...........................................................195 timer0 ...............................................................192 timer1 ...............................................................192 watchdog timer ................................................191 pic16c64a brown-out reset................................................207 capture/compare/pwm ....................................209 clkout and i/o ...............................................206 external clock ...................................................205 i 2 c bus data .....................................................213 i 2 c bus start/stop bits ......................................212 oscillator start-up timer ...................................207 parallel slave port.............................................210 power-up timer.................................................207 reset .................................................................207 spi mode...........................................................211 timer0 ...............................................................208 timer1 ...............................................................208 watchdog timer ................................................207 pic16c65 capture/compare/pwm ....................................225 clkout and i/o ...............................................222 external clock ...................................................221 i 2 c bus data .....................................................229 i 2 c bus start/stop bits ......................................228 oscillator start-up timer ...................................223 parallel slave port.............................................226 reset .................................................................223 spi mode...........................................................227 timer0 ...............................................................224 timer1 ...............................................................224 usart synchronous receive (master/slave) ...................................................230 watchdog timer ................................................223 pic16c65a brown-out reset................................................239 capture/compare/pwm ....................................241 clkout and i/o ...............................................238 external clock ...................................................237 i 2 c bus data .....................................................245
pic16c6x ds30234d-page 324 1997 microchip technology inc. i 2 c bus start/stop bits...................................... 244 oscillator start-up timer ................................... 239 parallel slave port ............................................ 242 power-up timer ................................................ 239 reset................................................................. 239 spi mode .......................................................... 243 timer0............................................................... 240 timer1............................................................... 240 usart synchronous receive (master/slave)................................................... 246 watchdog timer................................................ 239 pic16c66 brown-out reset ............................................... 271 capture/compare/pwm.................................... 273 clkout and i/o............................................... 270 external clock................................................... 269 i 2 c bus data ..................................................... 279 i 2 c bus start/stop bits...................................... 278 oscillator start-up timer ................................... 271 power-up timer ................................................ 271 reset................................................................. 271 timer0............................................................... 272 timer1............................................................... 272 usart synchronous receive (master/slave)................................................... 280 watchdog timer................................................ 271 pic16c67 brown-out reset ............................................... 271 capture/compare/pwm.................................... 273 clkout and i/o............................................... 270 external clock................................................... 269 i 2 c bus data ..................................................... 279 i 2 c bus start/stop bits...................................... 278 oscillator start-up timer ................................... 271 parallel slave port ............................................ 274 power-up timer ................................................ 271 reset................................................................. 271 timer0............................................................... 272 timer1............................................................... 272 usart synchronous receive (master/slave)................................................... 280 watchdog timer................................................ 271 pic16cr62 capture/compare/pwm.................................... 209 clkout and i/o............................................... 206 external clock................................................... 205 i 2 c bus data ..................................................... 213 i 2 c bus start/stop bits...................................... 212 oscillator start-up timer ................................... 207 power-up timer ................................................ 207 reset................................................................. 207 spi mode .......................................................... 211 timer0............................................................... 208 timer1............................................................... 208 watchdog timer................................................ 207 pic16cr63 brown-out reset............................................... 255 capture/compare/pwm ................................... 257 clkout and i/o .............................................. 254 external clock .................................................. 253 i 2 c bus data..................................................... 261 i 2 c bus start/stop bits ..................................... 260 oscillator start-up timer................................... 255 power-up timer ................................................ 255 reset ................................................................ 255 spi mode.......................................................... 259 timer0 .............................................................. 256 timer1 .............................................................. 256 usart synchronous receive (master/slave) ................................................. 262 watchdog timer ............................................... 255 pic16cr64 capture/compare/pwm ................................... 209 clkout and i/o .............................................. 206 external clock .................................................. 205 i 2 c bus data..................................................... 213 i 2 c bus start/stop bits ..................................... 212 oscillator start-up timer................................... 207 parallel slave port ............................................ 210 power-up timer ................................................ 207 reset ................................................................ 207 spi mode.......................................................... 211 timer0 .............................................................. 208 timer1 .............................................................. 208 watchdog timer ............................................... 207 pic16cr65 brown-out reset............................................... 255 capture/compare/pwm ................................... 257 clkout and i/o .............................................. 254 external clock .................................................. 253 i 2 c bus data..................................................... 261 i 2 c bus start/stop bits ..................................... 260 oscillator start-up timer................................... 255 parallel slave port ............................................ 258 power-up timer ................................................ 255 reset ................................................................ 255 spi mode.......................................................... 259 timer0 .............................................................. 256 timer1 .............................................................. 256 usart synchronous receive (master/slave) .................................................. 262 watchdog timer ............................................... 255 power-up timer ........................................................ 223 pwm output ............................................................... 80 rb0/int interrupt ..................................................... 138 rx pin sampling .............................................. 110, 111 spi master mode........................................................ 93 spi mode, master/slave mode, no ss control............................................................. 88 spi mode, slave mode with ss control .................... 88 spi slave mode (cke = 1) ......................................... 94 spi slave mode timing (cke = 0) ............................. 93 timer0 with external clock......................................... 67 tmr0 interrupt timing................................................ 66 usart asynchronous master transmission ........... 113 usart asynchronous master transmission (back to back) .......................................................... 113 usart asynchronous reception ............................ 114 usart synchronous reception in master mode............................................................. 119 usart synchronous tranmission........................... 117 wake-up from sleep through interrupts................ 142
1997 microchip technology inc. ds30234d-page 325 pic16c6x tmr0 .................................................... 24, 26, 28, 30, 32, 34 tmr0 clock source select bit, t0cs................................. 36 tmr0 interrupt.................................................................... 65 tmr0 overflow interrupt enable bit, t0ie .......................... 37 tmr0 overflow interrupt flag bit, t0if .............................. 37 tmr0 prescale selection table ......................................... 36 tmr0 source edge select bit, t0se.................................. 36 tmr1 overflow interrupt enable bit, tmr1ie .................... 38 tmr1 overflow interrupt flag bit, tmr1if ......................... 41 tmr1cs ............................................................................. 71 tmr1h.................................................. 24, 26, 28, 30, 32, 34 tmr1ie............................................................................... 38 tmr1if ............................................................................... 41 tmr1l .................................................. 24, 26, 28, 30, 32, 34 tmr1on............................................................................. 71 tmr2 .................................................... 24, 26, 28, 30, 32, 34 tmr2 register.................................................................... 75 tmr2 to pr2 match interrupt enable bit, tmr2ie............. 38 tmr2 to pr2 match interrupt flag bit, tmr2if ................. 41 tmr2ie............................................................................... 38 tmr2if ............................................................................... 41 tmr2on............................................................................. 75 to ............................................................................... 35, 131 toutps3:toutps0.......................................................... 75 transmit enable bit, txen ............................................... 105 transmit shift register status bit, trmt ......................... 105 transmit status and control register............................... 105 trisa ............................................. 25, 27, 29, 31, 33, 34, 51 trisb ............................................. 25, 27, 29, 31, 33, 34, 53 trisc ....................................... 25, 27, 29, 31, 33, 34, 55, 94 trisd ............................................. 25, 27, 29, 31, 33, 34, 57 trise ............................................. 25, 27, 29, 31, 33, 34, 58 trmt ................................................................................ 105 tx9 ................................................................................... 105 tx9d................................................................................. 105 txen ................................................................................ 105 txie .................................................................................... 39 txif .................................................................................... 42 txreg.................................................. 24, 26, 28, 30, 32, 34 txsta .......................................... 25, 27, 29, 31, 33, 34, 105 u ua ................................................................................. 84, 89 universal synchronous asynchronous receiver transmitter (usart) asynchronous mode setting up transmission................................... 113 timing diagram, master transmission ............. 113 transmitter........................................................ 112 asynchronous receiver setting up reception........................................ 115 timing diagram ................................................ 114 asynchronous receiver mode block diagram .................................................. 114 section.............................................................. 114 section ...................................................................... 105 synchronous master mode reception.......................................................... 118 section.............................................................. 116 setting up reception........................................ 118 setting up transmission................................... 116 timing diagram, reception .............................. 119 timing diagram, transmission ......................... 117 transmission .................................................... 116 synchronous slave mode reception ..........................................................120 section ..............................................................120 setting up reception ........................................120 setting up transmission ...................................120 transmit ............................................................120 transmit block diagram ............................................112 update address bit, ua .................................................84, 89 usart receive interrupt enable bit, rcie ........................39 usart receive interrupt flag bit, rcif.............................42 usart transmit interrupt enable bit, txie ........................39 usart transmit interrupt flag bit, txif ............................42 uv erasable devices.............................................................7 w wake-up from sleep..........................................................141 wake-up on key depression...............................................53 wake-up using interrupts..................................................141 watchdog timer (wdt) block diagram ...........................................................140 period ........................................................................140 programming considerations ....................................140 section.......................................................................140 wcol............................................................................85, 90 weak internal pull-ups ........................................................53 write collision detect bit, wcol...................................85, 90 x xmit_mode .....................................................................104 xt ......................................................................................130 z z ..........................................................................................35 zero bit ............................................................................9, 35
pic16c6x ds30234d-page 326 1997 microchip technology inc. list of equation and examples example 3-1: instruction pipeline flow............................. 18 example 4-1: call of a subroutine in page 1 from page 0 ................................................ 49 example 4-2: indirect addressing ..................................... 49 example 5-1: initializing porta....................................... 51 example 5-2: initializing portb....................................... 53 example 5-3: initializing portc ...................................... 55 example 5-4: read-modify-write instructions on an i/o port ....................................................... 60 example 7-1: changing prescaler (timer0 ? wdt) .......... 69 example 7-2: changing prescaler (wdt ? timer0) .......... 69 example 8-1: reading a 16-bit free-running timer ..................................... 73 example 10-1: changing between capture prescalers ..................................... 79 example 10-2: pwm period and duty cycle calculation ........................................ 81 example 11-1: loading the sspbuf (sspsr) register....................................... 86 example 11-2: loading the sspbuf (sspsr) register (pic16c66/67).............. 91 example 12-1: calculating baud rate error ..................... 107 example 13-1: saving status and w registers in ram...................................... 139 example 13-2: saving status, w, and pclath registers in ram (all other pic16c6x devices) ................... 139 list of figures figure 3-1: pic16c61 block diagram........................... 10 figure 3-2: pic16c62/62a/r62/64/64a/r64 block diagram ............................................ 11 figure 3-3: pic16c63/r63/65/65a/r65 block diagram ............................................ 12 figure 3-4: pic16c66/67 block diagram...................... 13 figure 3-5: clock/instruction cycle ............................... 18 figure 4-1: pic16c61 program memory map and stack.................................................... 19 figure 4-2: pic16c62/62a/r62/64/64a/ r64 program memory map and stack ....... 19 figure 4-3: pic16c63/r63/65/65a/r65 program memory map and stack.............................. 19 figure 4-4: pic16c66/67 program memory map and stack............................................ 20 figure 4-5: pic16c61 register file map ...................... 20 figure 4-6: pic16c62/62a/r62/64/64a/ r64 register file map ................................ 21 figure 4-7: pic16c63/r63/65/65a/r65 register file map........................................ 21 figure 4-8: pic16c66/67 data memory map................ 22 figure 4-9: status register (address 03h, 83h, 103h, 183h) ................. 35 figure 4-10: option register (address 81h, 181h) ................................... 36 figure 4-11: intcon register (address 0bh, 8bh, 10bh 18bh)................. 37 figure 4-12: pie1 register for pic16c62/62a/r62 (address 8ch)............................................. 38 figure 4-13: pie1 register for pic16c63/r63/66 (address 8ch)............................................. 39 figure 4-14: pie1 register for pic16c64/64a/r64 (address 8ch)............................................. 39 figure 4-15: pie1 register for pic16c65/65a/r65/67 (address 8ch) ............................................ 40 figure 4-16: pir1 register for pic16c62/62a/r62 (address 0ch) ............................................ 41 figure 4-17: pir1 register for pic16c63/r63/66 address 0ch) ............................................. 42 figure 4-18: pir1 register for pic16c64/64a/r64 (address 0ch) ............................................ 43 figure 4-19: pir1 register for pic16c65/65a/r65/67 (address 0ch) ............................................ 44 figure 4-20: pie2 register (address 8dh) ..................... 45 figure 4-21: pir2 register (address 0dh)..................... 46 figure 4-22: pcon register for pic16c62/64/65 (address 8eh) ............................................ 47 figure 4-23: pcon register for pic16c62a/r62/63/ r63/64a/r64/65a/r65/66/67 (address 8eh) ............................................ 47 figure 4-24: loading of pc in different situations ......... 48 figure 4-25: direct/indirect addressing .......................... 49 figure 5-1: block diagram of the ra3:ra0 pins and the ra5 pin ................. 51 figure 5-2: block diagram of the ra4/t0cki pin......... 51 figure 5-3: block diagram of the rb7:rb4 pins for pic16c61/62/64/65....... 53 figure 5-4: block diagram of the rb7:rb4 pins for pic16c62a/63/r63/ 64a/65a/r65/66/67 .................................... 54 figure 5-5: block diagram of the rb3:rb0 pins ............................................ 54 figure 5-6: portc block diagram .............................. 55 figure 5-7: portd block diagram (in i/o port mode)....................................... 57 figure 5-8: porte block diagram (in i/o port mode)...................................... 58 figure 5-9: trise register (address 89h)................... 58 figure 5-10: successive i/o operation........................... 60 figure 5-11: portd and porte as a parallel slave port................................................... 61 figure 5-12: parallel slave port write waveforms ......... 62 figure 5-13: parallel slave port read waveforms ......... 62 figure 7-1: timer0 block diagram................................ 65 figure 7-2: timer0 timing: internal clock/no prescaler .................................................... 65 figure 7-3: timer0 timing: internal clock/prescale 1:2 ..................................... 66 figure 7-4: tmr0 interrupt timing ............................... 66 figure 7-5: timer0 timing with external clock ............ 67 figure 7-6: block diagram of the timer0/wdt prescaler .................................................... 68 figure 8-1: t1con: timer1 control register (address 10h)............................................. 71 figure 8-2: timer1 block diagram................................ 72 figure 9-1: timer2 block diagram................................ 75 figure 9-2: t2con: timer2 control register (address 12h)............................................. 75 figure 10-1: ccp1con register (address 17h) / ccp2con register (address 1dh) ........... 78 figure 10-2: capture mode operation block diagram ............................................ 78 figure 10-3: compare mode operation block diagram ............................................ 79 figure 10-4: simplified pwm block diagram.................. 80 figure 10-5: pwm output............................................... 80 figure 11-1: sspstat: sync serial port status register (address 94h) .............................. 84
1997 microchip technology inc. ds30234d-page 327 pic16c6x figure 11-2: sspcon: sync serial port control register (address 14h) .................. 85 figure 11-3: ssp block diagram (spi mode) ................. 86 figure 11-4: spi master/slave connection..................... 87 figure 11-5: spi mode timing, master mode or slave mode w/o ss control........................ 88 figure 11-6: spi mode timing, slave mode with ss control .................................................. 88 figure 11-7: sspstat: sync serial port status register (address 94h)(pic16c66/67)....... 89 figure 11-8: sspcon: sync serial port control register (address 14h)(pic16c66/67)....... 90 figure 11-9: ssp block diagram (spi mode) (pic16c66/67)............................................ 91 figure 11-10: spi master/slave connection (pic16c66/67)............................................ 92 figure 11-11: spi mode timing, master mode (pic16c66/67)............................................ 93 figure 11-12: spi mode timing (slave mode with cke = 0) (pic16c66/67) ............................ 93 figure 11-13: spi mode timing (slave mode with cke = 1) (pic16c66/67) ............................ 94 figure 11-14: start and stop conditions........................... 95 figure 11-15: 7-bit address format .................................. 96 figure 11-16: i 2 c 10-bit address format .......................... 96 figure 11-17: slave-receiver acknowledge ...................... 96 figure 11-18: data transfer wait state ............................ 96 figure 11-19: master-transmitter sequence ..................... 97 figure 11-20: master-receiver sequence.......................... 97 figure 11-21: combined format ....................................... 97 figure 11-22: multi-master arbitration (two masters)............................................. 98 figure 11-23: clock synchronization ................................ 98 figure 11-24: ssp block diagram (i 2 c mode).................. 99 figure 11-25: i 2 c waveforms for reception (7-bit address) .......................................... 101 figure 11-26: i 2 c waveforms for transmission (7-bit address) .......................................... 102 figure 11-27: operation of the i 2 c module in idle_mode, rcv_mode or xmit_mode ............................................ 104 figure 12-1: txsta: transmit status and control register (address 98h) ................ 105 figure 12-2: rcsta: receive status and control register (address 18h) ................ 106 figure 12-3: rx pin sampling scheme (brgh = 0) pic16c63/r63/65/65a/r65) .................... 110 figure 12-4: rx pin sampling scheme (brgh = 1) (pic16c63/r63/65/65a/r65) ................... 110 figure 12-5: rx pin sampling scheme (brgh = 1) (pic16c63/r63/65/65a/r65) ................... 110 figure 12-6: rx pin sampling scheme (brgh = 0 or = 1) (pic16c66/67).......................................... 111 figure 12-7: usart transmit block diagram .............. 112 figure 12-8: asynchronous master transmission......... 113 figure 12-9: asynchronous master transmission (back to back) .......................................... 113 figure 12-10: usart receive block diagram ............... 114 figure 12-11: asynchronous reception.......................... 114 figure 12-12: synchronous transmission ...................... 117 figure 12-13: synchronous transmission through txen ........................................... 117 figure 12-14: synchronous reception (master mode, sren) .............................. 119 figure 13-1: configuration word for pic16c61 ............ 123 figure 13-2: configuration word for pic16c62/64/65........................................124 figure 13-3: configuration word for pic16c62a/r62/63/r63/64a/r64/ 65a/r65/66/67 ..........................................124 figure 13-4: crystal/ceramic resonator operation (hs, xt or lp osc configuration)............125 figure 13-5: external clock input operation (hs, xt or lp osc configuration)............125 figure 13-6: external parallel resonant crystal oscillator circuit ............................127 figure 13-7: external series resonant crystal oscillator circuit ............................127 figure 13-8: rc oscillator mode ...................................127 figure 13-9: simplified block diagram of on-chip reset circuit ................................128 figure 13-10: brown-out situations .................................129 figure 13-11: time-out sequence on power-up (mclr not tied to v dd ): case 1...............134 figure 13-12: time-out sequence on power-up (mclr not tied to v dd ): case 2 .............134 figure 13-13: time-out sequence on power-up (mclr tied to v dd ) ..................................134 figure 13-14: external power-on reset circuit (for slow v dd power-up)..........................135 figure 13-15: external brown-out protection circuit 1 ....................................135 figure 13-16: external brown-out protection circuit 2 ....................................135 figure 13-17: interrupt logic for pic16c61.....................137 figure 13-18: interrupt logic for pic16c6x ....................137 figure 13-19: int pin interrupt timing ............................138 figure 13-20: watchdog timer block diagram................140 figure 13-21: summary of watchdog timer registers .........................................140 figure 13-22: wake-up from sleep through interrupt.......................................142 figure 13-23: typical in-circuit serial programming connection..........................142 figure 14-1: general format for instructions.................143 figure 16-1: load conditions for device timing specifications ............................................168 figure 16-2: external clock timing ...............................169 figure 16-3: clkout and i/o timing ...........................170 figure 16-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing........................................................171 figure 16-5: timer0 external clock timings .................172 figure 17-1: typical rc oscillator frequency vs. temperature .....................173 figure 17-2: typical rc oscillator frequency vs. v dd ....................................174 figure 17-3: typical rc oscillator frequency vs. v dd ....................................174 figure 17-4: typical rc oscillator frequency vs. v dd ....................................174 figure 17-5: typical i pd vs. v dd watchdog timer disabled 25 c ...........................................174 figure 17-6: typical i pd vs. v dd watchdog timer enabled 25 c ............................................175 figure 17-7: maximum i pd vs. v dd watchdog disabled ....................................................175 figure 17-8: maximum i pd vs. v dd watchdog enabled*....................................................176 figure 17-9: v th (input threshold voltage) of i/o pins vs. v dd ........................................176
pic16c6x ds30234d-page 328 1997 microchip technology inc. figure 17-10: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd ............................... 177 figure 17-11: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd ............................ 177 figure 17-12: typical i dd vs. frequency (external clock, 25 c) .............................. 178 figure 17-13: maximum i dd vs. frequency (external clock, -40 to +85 c) ................ 178 figure 17-14: maximum i dd vs. frequency (external clock, -55 to +125 c) .............. 179 figure 17-15: wdt timer time-out period vs. v dd ........ 179 figure 17-16: transconductance (gm) of hs oscillator vs. v dd ...................................... 179 figure 17-17: transconductance (gm) of lp oscillator vs. v dd ...................................... 180 figure 17-18: transconductance (gm) of xt oscillator vs. v dd ...................................... 180 figure 17-19: i oh vs. v oh , v dd = 3v .............................. 180 figure 17-20: i oh vs. v oh , v dd = 5v .............................. 180 figure 17-21: i ol vs. v ol , v dd = 3v ............................... 181 figure 17-22: i ol vs. v ol , v dd = 5v ............................... 181 figure 18-1: load conditions for device timing specifications................................ 188 figure 18-2: external clock timing............................... 189 figure 18-3: clkout and i/o timing........................... 190 figure 18-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ............................ 191 figure 18-5: timer0 and timer1 external clock timings ........................................... 192 figure 18-6: capture/compare/pwm timings (ccp1)...................................................... 193 figure 18-7: parallel slave port timing (pic16c64)............................................... 194 figure 18-8: spi mode timing ...................................... 195 figure 18-9: i 2 c bus start/stop bits timing.................. 196 figure 18-10: i 2 c bus data timing ................................. 197 figure 19-1: load conditions for device timing specifications................................ 204 figure 19-2: external clock timing............................... 205 figure 19-3: clkout and i/o timing........................... 206 figure 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ............................ 207 figure 19-5: brown-out reset timing ........................... 207 figure 19-6: timer0 and timer1 external clock timings ........................................... 208 figure 19-7: capture/compare/pwm timings (ccp1)...................................................... 209 figure 19-8: parallel slave port timing (pic16c64a/r64)..................................... 210 figure 19-9: spi mode timing ...................................... 211 figure 19-10: i 2 c bus start/stop bits timing.................. 212 figure 19-11: i 2 c bus data timing ................................. 213 figure 20-1: load conditions for device timing specifications............................................ 220 figure 20-2: external clock timing............................... 221 figure 20-3: clkout and i/o timing........................... 222 figure 20-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ....................................................... 223 figure 20-5: timer0 and timer1 external clock timings ..................................................... 224 figure 20-6: capture/compare/pwm timings (ccp1 and ccp2) .................................... 225 figure 20-7: parallel slave port timing ........................ 226 figure 20-8: spi mode timing...................................... 227 figure 20-9: i 2 c bus start/stop bits timing ................. 228 figure 20-10: i 2 c bus data timing................................. 229 figure 20-11: usart synchronous transmission (master/slave) timing .............................. 230 figure 20-12: usart synchronous receive (master/slave) timing .............................. 230 figure 21-1: load conditions for device timing specifications ........................................... 236 figure 21-2: external clock timing .............................. 237 figure 21-3: clkout and i/o timing .......................... 238 figure 21-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing....................................................... 239 figure 21-5: brown-out reset timing........................... 239 figure 21-6: timer0 and timer1 external clock timings..................................................... 240 figure 21-7: capture/compare/pwm timings (ccp1 and ccp2)................................... 241 figure 21-8: parallel slave port timing (pic16c65a) ............................................ 242 figure 21-9: spi mode timing...................................... 243 figure 21-10: i 2 c bus start/stop bits timing ................. 244 figure 21-11: i 2 c bus data timing................................. 245 figure 21-12: usart synchronous transmission (master/slave) timing .............................. 246 figure 21-13: usart synchronous receive (master/slave) timing .............................. 246 figure 22-1: load conditions for device timing specifications ........................................... 252 figure 22-2: external clock timing .............................. 253 figure 22-3: clkout and i/o timing .......................... 254 figure 22-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing....................................................... 255 figure 22-5: brown-out reset timing........................... 255 figure 22-6: timer0 and timer1 external clock timings..................................................... 256 figure 22-7: capture/compare/pwm timings (ccp1 and ccp2).................................... 257 figure 22-8: parallel slave port timing (pic16cr65)............................................ 258 figure 22-9: spi mode timing...................................... 259 figure 22-10: i 2 c bus start/stop bits timing ................. 260 figure 22-11: i 2 c bus data timing................................. 261 figure 22-12: usart synchronous transmission (master/slave) timing .............................. 262 figure 22-13: usart synchronous receive (master/slave) timing .............................. 262 figure 23-1: load conditions for device timing specifications ........................................... 268 figure 23-2: external clock timing .............................. 269 figure 23-3: clkout and i/o timing .......................... 270 figure 23-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing....................................................... 271 figure 23-5: brown-out reset timing........................... 271 figure 23-6: timer0 and timer1 external clock timings..................................................... 272 figure 23-7: capture/compare/pwm timings (ccp1 and ccp2).................................... 273 figure 23-8: parallel slave port timing (pic16c67) .... 274 figure 23-9: spi master mode timing (cke = 0) ......... 275 figure 23-10: spi master mode timing (cke = 1) ......... 275 figure 23-11: spi slave mode timing (cke = 0) ........... 276
1997 microchip technology inc. ds30234d-page 329 pic16c6x figure 23-12: spi slave mode timing (cke = 1) ........... 276 figure 23-13: i 2 c bus start/stop bits timing.................. 278 figure 23-14: i 2 c bus data timing ................................. 279 figure 23-15: usart synchronous transmission (master/slave) timing............................... 280 figure 23-16: usart synchronous receive (master/slave) timing............................... 280 figure 24-1: typical i pd vs. v dd (wdt disabled, rc mode) ....................... 281 figure 24-2: maximum i pd vs. v dd (wdt disabled, rc mode) ....................... 281 figure 24-3: typical i pd vs. v dd @ 25 c (wdt enabled, rc mode)........................ 282 figure 24-4: maximum i pd vs. v dd (wdt enabled, rc mode)........................ 282 figure 24-5: typical rc oscillator frequency vs. v dd .................................... 282 figure 24-6: typical rc oscillator frequency vs. v dd .................................... 282 figure 24-7: typical rc oscillator frequency vs. v dd .................................... 282 figure 24-8: typical i pd vs. v dd brown-out detect enabled (rc mode)....................... 283 figure 24-9: maximum i pd vs. v dd brown-out detect enabled (85 c to -40 c, rc mode) ........................ 283 figure 24-10: typical i pd vs. timer1 enabled (32 khz, rc0/rc1 = 33 pf/33 pf, rc mode) ................................................ 283 figure 24-11: maximum i pd vs. timer1 enabled (32 khz, rc0/rc1 = 33 pf/33 pf, 85 c to -40 c, rc mode) ......................... 283 figure 24-12: typical i dd vs. frequency (rc mode @ 22 pf, 25 c) ....................... 284 figure 24-13: maximum i dd vs. frequency (rc mode @ 22 pf, -40 c to 85 c) ......... 284 figure 24-14: typical i dd vs. frequency (rc mode @ 100 pf, 25 c) ..................... 285 figure 24-15: maximum i dd vs. frequency (rc mode @ 100 pf, -40 c to 85 c) ....... 285 figure 24-16: typical i dd vs. frequency (rc mode @ 300 pf, 25 c) ..................... 286 figure 24-17: maximum i dd vs. frequency (rc mode @ 300 pf, -40 c to 85 c) ....... 286 figure 24-18: typical i dd vs. capacitance @ 500 khz (rc mode) ................................................ 287 figure 24-19: transconductance(gm) of hs oscillator vs. v dd ...................................... 287 figure 24-20: transconductance(gm) of lp oscillator vs. v dd ...................................... 287 figure 24-21: transconductance(gm) of xt oscillator vs. v dd ...................................... 287 figure 24-22: typical xtal startup time vs. v dd (lp mode, 25 c) ....................................... 288 figure 24-23: typical xtal startup time vs. v dd (hs mode, 25 c) ...................................... 288 figure 24-24: typical xtal startup time vs. v dd (xt mode, 25 c)....................................... 288 figure 24-25: typical idd vs. frequency (lp mode, 25 c) ....................................... 289 figure 24-26: maximum i dd vs. frequency (lp mode, 85 c to -40 c)......................... 289 figure 24-27: typical i dd vs. frequency (xt mode, 25 c)....................................... 289 figure 24-28: maximum i dd vs. frequency (xt mode, -40 c to 85 c) ........................ 289 figure 24-29: typical i dd vs. frequency (hs mode, 25 c) .......................................290 figure 24-30: maximum i dd vs. frequency (hs mode, -40 c to 85 c).........................290
pic16c6x ds30234d-page 330 1997 microchip technology inc. list of tables table 1-1: pic16c6x family of devices ....................... 6 table 3-1: pic16c61 pinout description ..................... 14 table 3-2: pic16c62/62a/r62/63/r63/66 pinout description....................................... 15 table 3-3: pic16c64/64a/r64/65/65a/r65/67 pinout description....................................... 16 table 4-1: special function registers for the pic16c61 ................................................... 23 table 4-2: special function registers for the pic16c62/62a/r62 .................................... 24 table 4-3: special function registers for the pic16c63/r63............................................ 26 table 4-4: special function registers for the pic16c64/64a/r64 .................................... 28 table 4-5: special function registers for the pic16c65/65a/r65 .................................... 30 table 4-6: special function registers for the pic16c66/67 .............................................. 32 table 5-1: porta functions....................................... 52 table 5-2: registers/bits associated with porta ....................................................... 52 table 5-3: portb functions....................................... 54 table 5-4: summary of registers associated with portb ....................................................... 54 table 5-5: portc functions for pic16c62/64........... 55 table 5-6: portc functions for pic16c62a/r62/64a/r64 .......................... 56 table 5-7: portc functions for pic16c63/r63/65/65a/r65/66/67.............. 56 table 5-8: summary of registers associated with portc ....................................................... 56 table 5-9: portd functions....................................... 57 table 5-10: summary of registers associated with portd ....................................................... 57 table 5-11: porte functions....................................... 59 table 5-12: summary of registers associated with porte ....................................................... 59 table 5-13: registers associated with parallel slave port ...................................... 62 table 7-1: registers associated with timer0 .............. 69 table 8-1: capacitor selection for the timer1 oscillator......................................... 73 table 8-2: registers associated with timer1 as a timer/counter ......................... 74 table 9-1: registers associated with timer2 as a timer/counter ......................... 76 table 10-1: ccp mode - timer resource ..................... 77 table 10-2: interaction of two ccp modules ................ 77 table 10-3: example pwm frequencies and resolutions at 20 mhz......................... 81 table 10-4: registers associated with timer1, capture and compare ................................ 81 table 10-5: registers associated with pwm and timer2.................................................. 82 table 11-1: registers associated with spi operation .................................................... 88 table 11-2: registers associated with spi operation (pic16c66/67) ........................... 94 table 11-3: i 2 c bus terminology................................... 95 table 11-4: data transfer received byte actions ...................................................... 100 table 11-5: registers associated with i 2 c operation .................................................. 103 table 12-1: baud rate formula................................... 107 table 12-2: registers associated with baud rate generator......................................... 107 table 12-3: baud rates for synchronous mode ......... 108 table 12-4: baud rates for asynchronous mode (brgh = 0)............................................... 108 table 12-5: baud rates for asynchronous mode (brgh = 1)............................................... 109 table 12-6: registers associated with asynchronous transmission .................... 113 table 12-7: registers associated with asynchronous reception ......................... 115 table 12-8: registers associated with synchronous master transmission .......... 117 table 12-9: registers associated with synchronous master reception ............... 118 table 12-10: registers associated with synchronous slave transmission ............ 121 table 12-11: registers associated with synchronous slave reception ................. 121 table 13-1: ceramic resonators pic16c61 ............... 126 table 13-2: ceramic resonators pic16c62/62a/r62/63/r63/ 64/64a/r64/65/65a/r65/66/67 ................ 126 table 13-3: capacitor selection for crystal oscillator for pic16c61............................ 126 table 13-4: capacitor selection for crystal oscillator for pic16c62/62a/r62/63/r63/ 64/64a/r64/65/65a/r65/66/67 ................ 126 table 13-5: time-out in various situations, pic16c61/62/64/65.................................. 130 table 13-6: time-out in various situations, pic16c62a/r62/63/r63/ 64a/r64/65a/r65/66/67 .......................... 130 table 13-7: status bits and their significance, pic16c61................................................. 130 table 13-8: status bits and their significance, pic16c62/64/65....................................... 130 table 13-9: status bits and their significance for pic16c62a/r62/63/r63/ 64a/r64/65a/r65/66/67 .......................... 131 table 13-10: reset condition for special registers on pic16c61/62/64/65............. 131 table 13-11: reset condition for special registers on pic16c62a/r62/63/r63/ 64a/r64/65a/r65/66/67 .......................... 131 table 13-12: initialization conditions for all registers.............................................. 132 table 14-1: opcode field descriptions ....................... 143 table 14-2: pic16cxx instruction set ........................ 144 table 15-1: development tools from microchip.......... 162 table 16-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) .............................. 163 table 16-2: external clock timing requirements ........................................... 169 table 16-3: clkout and i/o timing requirements ........................................... 170 table 16-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements ................ 171 table 16-5: timer0 external clock requirements....... 172 table 17-1: rc oscillator frequencies ....................... 173 table 17-2: input capacitance* ................................... 181
1997 microchip technology inc. ds30234d-page 331 pic16c6x table 18-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) .............................. 183 table 18-2: external clock timing requirements ........................................... 189 table 18-3: clkout and i/o timing requirements ........................................... 190 table 18-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements................. 191 table 18-5: timer0 and timer1 external clock requirements ................................. 192 table 18-6: capture/compare/pwm requirements (ccp1) .............................. 193 table 18-7: parallel slave port requirements (pic16c64)............................................... 194 table 18-8: spi mode requirements........................... 195 table 18-9: i 2 c bus start/stop bits requirements ........................................... 196 table 18-10: i 2 c bus data requirements ..................... 197 table 19-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) .............................. 199 table 19-2: external clock timing requirements ........................................... 205 table 19-3: clkout and i/o timing requirements ........................................... 206 table 19-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements ................................. 207 table 19-5: timer0 and timer1 external clock requirements ................................. 208 table 19-6: capture/compare/pwm requirements (ccp1) .............................. 209 table 19-7: parallel slave port requirements (pic16c64a/r64)..................................... 210 table 19-8: spi mode requirements........................... 211 table 19-9: i 2 c bus start/stop bits requirements ........................................... 212 table 19-10: i 2 c bus data requirements ..................... 213 table 20-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) .............................. 215 table 20-2: external clock timing requirements ........................................... 221 table 20-3: clkout and i/o timing requirements ........................................... 222 table 20-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements................. 223 table 20-5: timer0 and timer1 external clock requirements ................................. 224 table 20-6: capture/compare/pwm requirements (ccp1 and ccp2)............. 225 table 20-7: parallel slave port requirements............. 226 table 20-8: spi mode requirements........................... 227 table 20-9: i 2 c bus start/stop bits requirements ........................................... 228 table 20-10: i 2 c bus data requirements...................... 229 table 20-11: usart synchronous transmission requirements ........................................... 230 table 20-12: usart synchronous receive requirements ............................................230 table 21-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ...............................231 table 21-2: external clock timing requirements ............................................237 table 21-3: clkout and i/o timing requirements ............................................238 table 21-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements ................239 table 21-5: timer0 and timer1 external clock requirements ..................................240 table 21-6: capture/compare/pwm requirements (ccp1 and ccp2) .............241 table 21-7: parallel slave port requirements (pic16c65a) .............................................242 table 21-8: spi mode requirements ...........................243 table 21-9: i 2 c bus start/stop bits requirements ............................................244 table 21-10: i 2 c bus data requirements ......................245 table 21-11: usart synchronous transmission requirements......................246 table 21-12: usart synchronous receive requirements ...........................................246 table 22-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ...............................247 table 22-2: external clock timing requirements ............................................253 table 22-3: clkout and i/o timing requirements ............................................254 table 22-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements..................................255 table 22-5: timer0 and timer1 external clock requirements ..................................256 table 22-6: capture/compare/pwm requirements (ccp1 and ccp2) .............257 table 22-7: parallel slave port requirements (pic16cr65).............................................258 table 22-8: spi mode requirements ...........................259 table 22-9: i 2 c bus start/stop bits requirements ............................................260 table 22-10: i 2 c bus data requirements ......................261 table 22-11: usart synchronous transmission requirements ............................................262 table 22-12: usart synchronous receive requirements ...........................................262 table 23-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ...............................263 table 23-2: external clock timing requirements ............................................269 table 23-3: clkout and i/o timing requirements ............................................270 table 23-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements..................................271
pic16c6x ds30234d-page 332 1997 microchip technology inc. table 23-5: timer0 and timer1 external clock requirements ................................. 272 table 23-6: capture/compare/pwm requirements (ccp1 and ccp2)............. 273 table 23-7: parallel slave port requirements (pic16c67)............................................... 274 table 23-8: spi mode requirements........................... 277 table 23-9: i 2 c bus start/stop bits requirements ........................................... 278 table 23-10: i 2 c bus data requirements ..................... 279 table 23-11: usart synchronous transmission requirements ........................................... 280 table 23-12: usart synchronous receive requirements ........................................... 280 table 24-1: rc oscillator frequencies........................ 287 table 24-2: capacitor selection for crystal oscillators ................................................. 288 table e-1: pin compatible devices............................ 315
1997 microchip technology inc. ds30234d-page 333 pic16c6x the procedure to connect will vary slightly from country to country. please check with your local compuserve agent for details if you have a problem. compuserve service allow multiple users various baud rates depending on the local point of access. the following connect procedure applies in most loca- tions. 1. set your modem to 8-bit, no parity, and one stop (8n1). this is not the normal compuserve setting which is 7e1. 2. dial your local compuserve access number. 3. depress the key and a garbage string will appear because compuserve is expecting a 7e1 setting. 4. type +, depress the key and host name: will appear. 5. type mchipbbs, depress the key and you will be connected to the microchip bbs. in the united states, to ?d the compuserve phone number closest to you, set your modem to 7e1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. after the system responds with host name: ? type network , depress the key and follow compuserve's directions. for voice information (or calling from overseas), you may call (614) 723-1550 for your local compuserve number. microchip regularly uses the microchip bbs to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for microchip systems software products. for each sig, a moderator monitors, scans, and approves or disap- proves ?es submitted to the sig. no executable ?es are accepted from the user community in general to limit the spread of computer viruses. systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy lab, are trademarks and sqtp is a service mark of microchip in the u.s.a. fuzzy tech is a registered trademark of inform software corporation. ibm, ibm pc-at are registered trademarks of international business machines corp. pentium is a trademark of intel corporation. windows is a trademark and ms-dos, microsoft windows are registered trade- marks of microsoft corporation. compuserve is a regis- tered trademark of compuserve incorporated. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides two methods of on-line support. these are the microchip bbs and the microchip world wide web (www) site. use microchip's bulletin board service (bbs) to get current information and help about microchip products. microchip provides the bbs communication channel for you to use in extending your technical staff with microcontroller and memory experts. to provide you with the most responsive service possible, the microchip systems team monitors the bbs, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how microchip products pro- vide project solutions. the web site, like the bbs, is used by microchip as a means to make ?es and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the ?e transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.futureone.com/pub/microchip the web site and ?e transfer site provide a variety of services. users may download ?es for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip speci? 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pic16c6x ds30234d-page 334 1997 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30234d pic16c6x
to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory o r the listed sales of?es. * jw devices are uv erasable and can be programmed to any device con?uration. jw devices meet the electrical requirement of each oscillator type (including lc devices). sales and suppor t products supported by a preliminary data sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. the microchip website at www.microchip.com 2. your local microchip sales of?e (see following page) 3. the microchip corporate literature center u.s. fax: (602) 786-7277 4. the microchips bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. for latest version information and upgrade kits for microchip development tools, please call 1-800-755-2345 or 1-602-786-7302. pattern: 3-digit pattern code for qtp (blank otherwise) package: l = plcc sp = skinny dip p = pdip so = soic (gull wing, 300 mil body) pq = mqfp (metric pqfp) tq = tqfp jw* = windowed cerdip ss = shrink soic (gull wing, 300 mil body) temperature - = 0?c to +70?c (t for tape/reel) range: i = ?40?c to +85?c (s for tape/reel) e = ?40?c to +125?c frequency 04 = 200 khz (pic16c6x-04) range: 04 = 4 mhz 10 = 10 mhz 20 = 20 mhz device: pic16c6x :v dd range 4.0v to 6.0v pic16c6xt :v dd range 4.0v to 6.0v (tape and reel) pic16lc6x :v dd range 2.5v to 6.0v pic16lc6xt :v dd range 2.5v to 6.0v (tape and reel) pic16cr6x :v dd range 4.0v to 6.0v pic16cr6xt :v dd range 4.0v to 6.0v (tape and reel) pic16lcr6x :v dd range 2.5v to 6.0v pic16lcr6xt:v dd range 2.5v to 6.0v part no. -xx x /xx xxx examples: a)pic16c62a - 04/p 301 = commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301 b)pic16lc65a - 04i/pq = industrial temp., mqfp package, 4 mhz, extended v dd limits c)pic16c67 - 10e/p = extended temp., pdip package, 10 mhz, normal v dd limits pic16c6x 1997 microchip technology inc. ds30234d-page 335 pic16c6x pr oduct identi cation system
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